{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,6]],"date-time":"2025-08-06T12:40:19Z","timestamp":1754484019385},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/dtis.2014.6850650","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T18:24:23Z","timestamp":1406658263000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["An electrostatically doped planar device concept"],"prefix":"10.1109","author":[{"given":"Tillmann","family":"Krauss","sequence":"first","affiliation":[]},{"given":"Frank","family":"Wessely","sequence":"additional","affiliation":[]},{"given":"Udo","family":"Schwalke","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2012.6232949"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/16\/9\/011"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2290555"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2008011"},{"year":"2013","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1002\/pssr.201307247"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2012.04.017"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2012.08.004"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1116\/1.2891257"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2010.05.013"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509585"},{"key":"12","article-title":"Process\/design co-optimization of regular logic tiles for double-Gate silicon nanowire transistors","author":"shashikanth","year":"2012","journal-title":"Proceedings of the IEEE \/ACM International Symposium on Nanoscale Architectures"}],"event":{"name":"2014 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2014,5,6]]},"location":"Santorini, Greece","end":{"date-parts":[[2014,5,8]]}},"container-title":["2014 9th IEEE International Conference on Design &amp; Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6844517\/6850634\/06850650.pdf?arnumber=6850650","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T17:49:23Z","timestamp":1490291363000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6850650\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dtis.2014.6850650","relation":{},"subject":[],"published":{"date-parts":[[2014,5]]}}}