{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:50:06Z","timestamp":1725472206281},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/dtis.2014.6850662","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T14:24:23Z","timestamp":1406643863000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["ATPG for transition faults of pipelined threshold logic circuits"],"prefix":"10.1109","author":[{"given":"Ashok kumar","family":"Palaniswamy","sequence":"first","affiliation":[]},{"given":"Spyros","family":"Tragoudas","sequence":"additional","affiliation":[]},{"given":"Themistoklis","family":"Haniotakis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/2287696.2287702"},{"key":"17","first-page":"384","article-title":"Atpg for path delay faults without path enumeration","author":"michael","year":"2001","journal-title":"Proc International Symposium on Quality Electronic Design"},{"journal-title":"Delay Fault Testing for VLSI Circuits","year":"2012","author":"krstic","key":"18"},{"journal-title":"Nanopipelined Threshold Synthesis Using Gate Replication","year":"2011","author":"pierce","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/2564924"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2100232"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/2206781.2206856"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.923432"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.44"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878291"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/GENSIPS.2007.4365826"},{"journal-title":"Threshold Logic and Its Applications","year":"1971","author":"muroga","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839468"},{"key":"7","first-page":"932","article-title":"Delay analysis of neuron mos and capacitive threshold logic","author":"celinski","year":"2000","journal-title":"Proc 5th IEEE Int Conf Electronics Circuits Systems"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2001.924554"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/5.752518"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.34"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2004.1333337"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/SCS.2003.1227096"}],"event":{"name":"2014 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2014,5,6]]},"location":"Santorini, Greece","end":{"date-parts":[[2014,5,8]]}},"container-title":["2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6844517\/6850634\/06850662.pdf?arnumber=6850662","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T13:49:24Z","timestamp":1490276964000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6850662\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dtis.2014.6850662","relation":{},"subject":[],"published":{"date-parts":[[2014,5]]}}}