{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:56:17Z","timestamp":1729641377833,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/dtis.2014.6850673","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T18:24:23Z","timestamp":1406658263000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA"],"prefix":"10.1109","author":[{"given":"Vinod","family":"Pangracious","sequence":"first","affiliation":[]},{"given":"Zied","family":"Marrakchi","sequence":"additional","affiliation":[]},{"given":"Nizar","family":"Beltaief","sequence":"additional","affiliation":[]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[]},{"given":"Umer","family":"Farooq","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007473"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117219"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/121404"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/368640.368739"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/259837"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36812-7_19"},{"key":"5","doi-asserted-by":"crossref","DOI":"10.1155\/2008\/764942","article-title":"Architecture level exploration of alternative schmes targeting 3D FPGAs: A software supported methodology","volume":"2008","author":"siozios","year":"2008","journal-title":"International Journal of Reconfigurable Computing"},{"key":"4","doi-asserted-by":"crossref","first-page":"1132","DOI":"10.1109\/TCAD.2005.855945","article-title":"Placement and routing in 3D integrated circuits","volume":"25","author":"ababei","year":"2003","journal-title":"IEEE Design and Test of Computers"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508203"},{"key":"8","first-page":"90","article-title":"Through silicon via-based grid for thermal control in 3D chips","volume":"2","author":"ayala","year":"2009","journal-title":"NanoNet Springer"},{"journal-title":"International Technology Road Map for Semiconductors-Interconnect TSV Roadmap","first-page":"17","year":"2012","key":"11"}],"event":{"name":"2014 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2014,5,6]]},"location":"Santorini, Greece","end":{"date-parts":[[2014,5,8]]}},"container-title":["2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6844517\/6850634\/06850673.pdf?arnumber=6850673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T17:30:40Z","timestamp":1498152640000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6850673\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/dtis.2014.6850673","relation":{},"subject":[],"published":{"date-parts":[[2014,5]]}}}