{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:44:07Z","timestamp":1729637047603,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/dtis.2015.7127349","type":"proceedings-article","created":{"date-parts":[[2015,6,18]],"date-time":"2015-06-18T16:07:41Z","timestamp":1434643661000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Scan-chain intra-cell defects grading"],"prefix":"10.1109","author":[{"given":"A.","family":"Touati","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Bosio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Dilillo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Girard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Virazel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Bernardi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. Sonza","family":"Reorda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401533"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2323216"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2009.5012098"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1007\/b117406","author":"bushnell","year":"2002","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2014.6868814"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2014.58"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529889"},{"key":"ref2","article-title":"Towards a World Without Test Escapes","author":"eichenberger","year":"2008","journal-title":"IEEE International Test Conference"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1748","DOI":"10.1109\/TCAD.2005.852457","article-title":"Diagnosis of Resistive-Open and Stuck-Open Defects in Digital CMOS ICs","volume":"24","author":"li","year":"2005","journal-title":"IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref1","first-page":"290","article-title":"Systematic defects in deep sub-micron technologies","author":"kruseman","year":"2005","journal-title":"IEEE International Test Conference"}],"event":{"name":"2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2015,4,21]]},"location":"Napoli, Italy","end":{"date-parts":[[2015,4,23]]}},"container-title":["2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7118811\/7127334\/07127349.pdf?arnumber=7127349","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,27]],"date-time":"2019-08-27T04:16:27Z","timestamp":1566879387000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7127349\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/dtis.2015.7127349","relation":{},"subject":[],"published":{"date-parts":[[2015,4]]}}}