{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:38:22Z","timestamp":1729611502833,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/dtis.2016.7483890","type":"proceedings-article","created":{"date-parts":[[2016,6,2]],"date-time":"2016-06-02T13:07:27Z","timestamp":1464872847000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach"],"prefix":"10.1109","author":[{"given":"Umer","family":"Farooq","sequence":"first","affiliation":[]},{"given":"M. Khurram","family":"Bhatti","sequence":"additional","affiliation":[]},{"given":"M. Hassan","family":"Aslam","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Incorporating memristors in currently established logic circuit architectures: Design considerations and challenges","author":"vourkas","year":"2014","journal-title":"workshop on Memristor Technology Design Automation and Computing (MemTDAC) affiliated with the HiPEAC 2014 conference"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/NANOARCH.2011.5941476"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1038\/nature06932"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TCSI.2009.2038539"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/ICCD.2011.6081389"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/CNNA.2012.6331426"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/TCSII.2014.2357292"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/INTECH.2015.7173484"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/ISCAS.2010.5537010"},{"key":"ref19","first-page":"945","article-title":"Reliable spice simulations of memristors, memcapacitors and meminductors","volume":"22","author":"biolek","year":"2013","journal-title":"Radioengineering"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1145\/1117201.1117204"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/FCCM.2004.21"},{"year":"2015","article-title":"Altera","key":"ref6"},{"year":"2015","article-title":"Xilinx","key":"ref5"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/MSPEC.2008.4687366"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TCT.1971.1083337"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1155\/2011\/121404"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1561\/1000000005","article-title":"Fpga architecture: Survey and challenges","volume":"2","author":"kuon","year":"2008","journal-title":"Found Trends Electron Des Autom"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ACCESS.2013.2259891"},{"year":"0","article-title":"Berkeley logic synthesis and verification group, university of california, berkeley. berkeley logic interchange format (blif)","key":"ref20"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1145\/296399.296426"},{"key":"ref21","article-title":"Sis: A system for sequential circuit analysis","author":"sentovich","year":"1992","journal-title":"Tech Report UCB ERL"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1145\/201310.201328"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"}],"event":{"name":"2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2016,4,12]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2016,4,14]]}},"container-title":["2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7480180\/7483795\/07483890.pdf?arnumber=7483890","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T11:36:22Z","timestamp":1498304182000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7483890\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/dtis.2016.7483890","relation":{},"subject":[],"published":{"date-parts":[[2016,4]]}}}