{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:48:34Z","timestamp":1761562114273},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/dtis.2016.7483892","type":"proceedings-article","created":{"date-parts":[[2016,6,2]],"date-time":"2016-06-02T13:07:27Z","timestamp":1464872847000},"page":"1-5","source":"Crossref","is-referenced-by-count":7,"title":["Multilevel operation in oxide based resistive RAM with SET voltage modulation"],"prefix":"10.1109","author":[{"given":"H.","family":"Aziza","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Ayari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Onkaraiah","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Moreau","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J-M.","family":"Portal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Bocquet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2202319"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea4010001"},{"key":"ref12","first-page":"3","article-title":"Investigation of the Impact of the Oxide Thickness and RESET conditions on Disturb in HfO2-RRAM integrated in a 65nm CMOS Technology","author":"diokh","year":"2013","journal-title":"International Reliability Physics Symposium"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/am.2013.81"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1149\/2.0061508ssl"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NVMTS.2011.6137089"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2006.1708695"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2014.6850647"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724674"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2253329"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s12668-014-0132-y"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488867"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177078"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2014.7038588"},{"key":"ref1","article-title":"Assessment of the Potential & Maturity of Selected Emerging Research Memory Technologies","author":"hutchby","year":"2010","journal-title":"ITRS - ERD\/ERM Technology Work Groups Report on Emerging Research Memory Technologies"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1063\/1.1831560"}],"event":{"name":"2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2016,4,12]]},"location":"Istanbul","end":{"date-parts":[[2016,4,14]]}},"container-title":["2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7480180\/7483795\/07483892.pdf?arnumber=7483892","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,27]],"date-time":"2016-09-27T22:54:40Z","timestamp":1475016880000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7483892\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/dtis.2016.7483892","relation":{},"subject":[],"published":{"date-parts":[[2016,4]]}}}