{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:21:50Z","timestamp":1730215310074,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1109\/dtis.2018.8368573","type":"proceedings-article","created":{"date-parts":[[2018,5,31]],"date-time":"2018-05-31T22:25:11Z","timestamp":1527805511000},"page":"1-2","source":"Crossref","is-referenced-by-count":0,"title":["SIC pair generation in near-optimal time with carry-look ahead adders"],"prefix":"10.1109","author":[{"given":"I.","family":"Voyiatzis","sequence":"first","affiliation":[]},{"given":"C.","family":"Efstathiou","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510873"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1997.599448"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.720322"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2000.840889"},{"key":"ref14","first-page":"201","article-title":"A BIST scheme for FPGA interconnect delay faults","author":"wang","year":"2005","journal-title":"Proceeding of 23rd VLSI Test Symposium 2005"},{"key":"ref15","first-page":"309","article-title":"Model for Delay Faults based Upon Paths","author":"smith","year":"1984","journal-title":"IEEE International Test Conference"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292298"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2000.856623"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.2000.873772"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.857159"},{"key":"ref4","first-page":"126","article-title":"Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-open Faults","author":"craig","year":"1985","journal-title":"IEEE international conference"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"1715","DOI":"10.1109\/PROC.1986.13687","article-title":"MOS VSI Reliability and Yield Trends","volume":"74","author":"woods","year":"1986","journal-title":"Proceedings of the IEEE"},{"key":"ref6","first-page":"309","article-title":"Built-In Test for CMOS Circuits","author":"starke","year":"1984","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19949812"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2007.4341532"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/APASIC.2000.896969"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1978.tb02106.x"},{"journal-title":"Digital Systems Testing and Testable Design","year":"1990","author":"abramovici","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1994.326863"}],"event":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","start":{"date-parts":[[2018,4,9]]},"location":"Taormina","end":{"date-parts":[[2018,4,12]]}},"container-title":["2018 13th International Conference on Design &amp; Technology of Integrated Systems In Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8362838\/8368541\/08368573.pdf?arnumber=8368573","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T05:30:06Z","timestamp":1643175006000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8368573\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dtis.2018.8368573","relation":{},"subject":[],"published":{"date-parts":[[2018,4]]}}}