{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:24:27Z","timestamp":1775003067581,"version":"3.50.1"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,6,28]]},"DOI":"10.1109\/dtis53253.2021.9505078","type":"proceedings-article","created":{"date-parts":[[2021,8,9]],"date-time":"2021-08-09T22:06:49Z","timestamp":1628546809000},"page":"1-6","source":"Crossref","is-referenced-by-count":26,"title":["FeFET based Logic-in-Memory: an overview"],"prefix":"10.1109","author":[{"given":"Cedric","family":"Marchand","sequence":"first","affiliation":[]},{"given":"Ian","family":"O'Connor","sequence":"additional","affiliation":[]},{"given":"Mayeul","family":"Cantan","sequence":"additional","affiliation":[]},{"given":"Evelyn T.","family":"Breyer","sequence":"additional","affiliation":[]},{"given":"Stefan","family":"Slesazeck","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Mikolajick","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2016.07.006"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351408"},{"key":"ref13","first-page":"1","article-title":"The impact of ferroelectric fets on digital and analog circuits and architectures","author":"chen","year":"2019","journal-title":"IEEE Design Test"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2871119"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2874880"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1063\/1.351910"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2889225"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2020.2987084"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2292055"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342199"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0092-2"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446059"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008501"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"2248","DOI":"10.1002\/adfm.201202383","article-title":"Beyond vonneumann computing with nanoscale phase-change memory devices","volume":"23","author":"wright","year":"2013","journal-title":"Advanced Functional Materials"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412960"},{"key":"ref2","first-page":"191","author":"talati","year":"2020","journal-title":"mMPU—A Real Processing-in-Memory Architecture to Combat the von Neumann Bottleneck"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2018.8644809"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614527"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0321-3"},{"key":"ref23","article-title":"Emerging technologies: Challenges and opportunities for logic synthesis","author":"bosio","year":"2021","journal-title":"24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems"}],"event":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","location":"Montpellier, France","start":{"date-parts":[[2021,6,28]]},"end":{"date-parts":[[2021,6,30]]}},"container-title":["2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9505031\/9505022\/09505078.pdf?arnumber=9505078","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:44:43Z","timestamp":1652197483000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9505078\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,28]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/dtis53253.2021.9505078","relation":{},"subject":[],"published":{"date-parts":[[2021,6,28]]}}}