{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T04:49:43Z","timestamp":1745988583315,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,6,28]]},"DOI":"10.1109\/dtis53253.2021.9505096","type":"proceedings-article","created":{"date-parts":[[2021,8,9]],"date-time":"2021-08-09T18:06:49Z","timestamp":1628532409000},"page":"1-5","source":"Crossref","is-referenced-by-count":4,"title":["On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions"],"prefix":"10.1109","author":[{"given":"Pietro","family":"Inglese","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elena Ioana","family":"Vatajelu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giorgio","family":"Di Natale","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"2054","DOI":"10.1109\/TVLSI.2013.2282132","article-title":"Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies","volume":"22","author":"kvatinsky","year":"2014","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1038\/nature08940"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TCSII.2015.2433536"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/TCSII.2014.2357292"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1038\/s41598-019-51039-6"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/3240765.3240811"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TNANO.2016.2570248"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/NANOARCH.2009.5226356"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/VLSI-SOC46417.2020.9344095"},{"key":"ref1","article-title":"Logic-In-Memory Implementations: A Comparison","author":"inglese","year":"2021","journal-title":"presented at the 2021 16th Conference on Ph D Research in Microelectronics and Electronics (PRIME)"}],"event":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2021,6,28]]},"location":"Montpellier, France","end":{"date-parts":[[2021,6,30]]}},"container-title":["2021 16th International Conference on Design &amp; Technology of Integrated Systems in Nanoscale Era (DTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9505031\/9505022\/09505096.pdf?arnumber=9505096","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T11:44:43Z","timestamp":1652183083000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9505096\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,28]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/dtis53253.2021.9505096","relation":{},"subject":[],"published":{"date-parts":[[2021,6,28]]}}}