{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T22:43:10Z","timestamp":1768344190445,"version":"3.49.0"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,10,14]],"date-time":"2024-10-14T00:00:00Z","timestamp":1728864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,10,14]],"date-time":"2024-10-14T00:00:00Z","timestamp":1728864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,10,14]]},"DOI":"10.1109\/dttis62212.2024.10780382","type":"proceedings-article","created":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T18:49:01Z","timestamp":1734115741000},"page":"1-7","source":"Crossref","is-referenced-by-count":3,"title":["Power Consumption Reduction in Integrated Pacemakers: Design Strategies for Cortex-M0+ Processors"],"prefix":"10.1109","author":[{"given":"Wafa","family":"Zitouni","sequence":"first","affiliation":[{"name":"Aix-Marseille Univ, Univ Toulon,CNRS, IM2NP,Marseille,France"}]},{"given":"R\u00e9my","family":"Vauche","sequence":"additional","affiliation":[{"name":"Aix-Marseille Univ, Univ Toulon,CNRS, IM2NP,Marseille,France"}]},{"given":"Hassen","family":"Aziza","sequence":"additional","affiliation":[{"name":"Aix-Marseille Univ, Univ Toulon,CNRS, IM2NP,Marseille,France"}]},{"given":"Laila","family":"Ayache","sequence":"additional","affiliation":[{"name":"Cairdac,Antony,France,92160"}]},{"given":"Alaa","family":"Makdissi","sequence":"additional","affiliation":[{"name":"Cairdac,Antony,France,92160"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.4304\/jcp.3.8.49-57"},{"key":"ref2","first-page":"236","article-title":"Design Overview of Low Power Implantable Pacemaker Using MSP 430F1612","volume-title":"SPIT-IEEE Colloquium and International Conference","volume":"2","author":"Chede"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DTTIS59576.2023.10348200"},{"key":"ref4","article-title":"The Definitive Guide to ARM Cortex-M0 and Cortex-M0+ Processors","author":"Yiu","year":"2015"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922072"},{"key":"ref6","article-title":"Design and analysis of custom standard-cell library for mixed signal applications","author":"Lakshmannan","year":"2022"},{"key":"ref7","article-title":"Power Consumption in CMOS","author":"Ng","year":"2022"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2011.2177256"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-022-06904-2"},{"key":"ref10","volume-title":"CAIRDAC\u2019s pacemaker"},{"issue":"4","key":"ref11","first-page":"31","article-title":"Leakage power reduction technique in CMOS Circuit: a state-of-the-art review","volume":"5","author":"Asija","year":"2015","journal-title":"Journal of VLSI and Signal Processing (IOSR-JVSP)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2185303"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842810"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ETI4.051663.2021.9619434"},{"key":"ref15","volume-title":"ARM Cortex-M0+ IP"},{"key":"ref16","volume-title":"Euro Practice IC Service Schedules & Prices 2024"},{"key":"ref17","volume-title":"Euro Practice IC Service Schedules & Prices 2021"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2013.6662149"},{"key":"ref19","article-title":"Capacitance and Power Modelling at Logic-Level","author":"Martins"},{"key":"ref20","article-title":"Extending OpenMSP430 Microcontroller for IoT Low-power Applications","author":"Cavaleiro","year":"2018"},{"key":"ref21","volume-title":"Corstone-101"}],"event":{"name":"2024 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)","location":"Aix-EN-PROVENCE, France","start":{"date-parts":[[2024,10,14]]},"end":{"date-parts":[[2024,10,16]]}},"container-title":["2024 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10779589\/10779988\/10780382.pdf?arnumber=10780382","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,10]],"date-time":"2025-02-10T18:28:15Z","timestamp":1739212095000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10780382\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,14]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dttis62212.2024.10780382","relation":{},"subject":[],"published":{"date-parts":[[2024,10,14]]}}}