{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T01:17:46Z","timestamp":1725499066631},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/ecctd.2007.4529560","type":"proceedings-article","created":{"date-parts":[[2008,5,29]],"date-time":"2008-05-29T17:43:50Z","timestamp":1212083030000},"page":"156-159","source":"Crossref","is-referenced-by-count":3,"title":["A switching noise vision of the optimization techniques for low-power synthesis"],"prefix":"10.1109","author":[{"given":"Javier","family":"Castro","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pilar","family":"Parra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel","family":"Valencia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio J.","family":"Acosta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"15"},{"year":"0","key":"13"},{"year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2004.1283688"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1117\/12.608276"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268919"},{"journal-title":"PrimePower Manual V-2004 06 June 2004","year":"0","key":"2"},{"year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2002.1187145"},{"key":"7","first-page":"862","article-title":"low power synthesis of dynamic logic circuits using finegrained clock gating","author":"banerjee","year":"2006","journal-title":"DATE"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3013-5"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1150343.1150400"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2004.09.003"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855952"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.102"}],"event":{"name":"2007 European Conference on Circuit Theory and Design (ECCTD 2007)","start":{"date-parts":[[2007,8,27]]},"location":"Sevilla, Spain","end":{"date-parts":[[2007,8,30]]}},"container-title":["2007 18th European Conference on Circuit Theory and Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4520033\/4529518\/04529560.pdf?arnumber=4529560","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T17:26:36Z","timestamp":1489685196000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4529560\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ecctd.2007.4529560","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}