{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T23:05:15Z","timestamp":1747868715620},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/ecctd.2007.4529730","type":"proceedings-article","created":{"date-parts":[[2008,5,29]],"date-time":"2008-05-29T13:43:50Z","timestamp":1212068630000},"page":"850-853","source":"Crossref","is-referenced-by-count":7,"title":["Synthesis of threshold logic circuits using tree matching"],"prefix":"10.1109","author":[{"given":"Tejaswi","family":"Gowda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuel","family":"Leshner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sarma","family":"Vrudhula","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Goran","family":"Konjevod","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Threshold Logic","year":"1965","author":"winder","key":"17"},{"key":"15","first-page":"222","article-title":"a non-ilp based threshold logic synthesis methodology","author":"gowda","year":"2007","journal-title":"Proc of the 16th IWLS"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228813"},{"key":"13","article-title":"synthesis of majority and minority networks and its applications to qca, tpl and set based nanotechnologies","author":"zhang","year":"0","journal-title":"VLSID'05"},{"key":"14","article-title":"threshold network synthesis and optimization and its application to nanotechnologies","author":"zhang","year":"2005","journal-title":"IEEE Trans CAD"},{"journal-title":"Threshold Logic and Its Applications","year":"1971","author":"muroga","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/5.663544"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2004.1333337"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185211"},{"year":"2003","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/5.752518"},{"journal-title":"Logic Synthesis and Verification Algorithms","year":"1996","author":"hachtel","key":"7"},{"journal-title":"Threshold Logic A Synthesis Approach","year":"1965","author":"dertouzos","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878291"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.818338"},{"journal-title":"Switching and Finite Automata Theory","year":"1970","author":"kohavi","key":"9"},{"journal-title":"Algorithm Design","year":"2005","author":"kleinberg","key":"8"}],"event":{"name":"2007 European Conference on Circuit Theory and Design (ECCTD 2007)","start":{"date-parts":[[2007,8,27]]},"location":"Sevilla, Spain","end":{"date-parts":[[2007,8,30]]}},"container-title":["2007 18th European Conference on Circuit Theory and Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4520033\/4529518\/04529730.pdf?arnumber=4529730","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T17:29:17Z","timestamp":1489685357000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4529730\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/ecctd.2007.4529730","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}