{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:34:39Z","timestamp":1730216079674,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,8]]},"DOI":"10.1109\/ecctd.2009.5274946","type":"proceedings-article","created":{"date-parts":[[2009,10,6]],"date-time":"2009-10-06T19:06:22Z","timestamp":1254855982000},"page":"193-196","source":"Crossref","is-referenced-by-count":11,"title":["A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology"],"prefix":"10.1109","author":[{"given":"Piotr","family":"Dudek","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexey","family":"Lopich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Viktor","family":"Gruev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/82.842115"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.848080"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.848106"},{"key":"15","first-page":"270","article-title":"neuromorphic vision chip fabricated using three-dimensional integration technology","volume":"1","author":"koyanagy","year":"2001","journal-title":"IEEE International Solid-State Circuits Conference ISSCC 2001"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378668"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4550025"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494016"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007158"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2000.892749"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1049\/el:20060352"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.840093"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5267-3"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848029"},{"key":"7","first-page":"337","article-title":"a compact computational core for image processing","volume":"1","author":"paasio","year":"2001","journal-title":"Proc ECC 2001"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/4.222178"},{"key":"5","article-title":"asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array","author":"lopich","year":"0","journal-title":"Int Journal of Circuit Theory and Applications"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541737"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511754494"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.827621"}],"event":{"name":"2009 European Conference on Circuit Theory and Design (ECCTD 2009)","start":{"date-parts":[[2009,8,23]]},"location":"Antalya, Turkey","end":{"date-parts":[[2009,8,27]]}},"container-title":["2009 European Conference on Circuit Theory and Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5247537\/5274921\/05274946.pdf?arnumber=5274946","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,17]],"date-time":"2021-06-17T20:08:51Z","timestamp":1623960531000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5274946\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,8]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/ecctd.2009.5274946","relation":{},"subject":[],"published":{"date-parts":[[2009,8]]}}}