{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T03:50:19Z","timestamp":1725681019430},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,8]]},"DOI":"10.1109\/ecctd.2009.5275114","type":"proceedings-article","created":{"date-parts":[[2009,10,6]],"date-time":"2009-10-06T19:06:22Z","timestamp":1254855982000},"page":"839-842","source":"Crossref","is-referenced-by-count":2,"title":["An efficient FPGA implementation of a DT-CNN for small image gray-scale pre-processing"],"prefix":"10.1109","author":[{"given":"J.","family":"Albo-Canals","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose A.","family":"Villasante-Bembibre","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jordi","family":"Riera-Babures","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N. A.","family":"Fernandez-Garcia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor M.","family":"Brea","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"3"},{"journal-title":"Split and Shift Techniques for CNN Hardware Reduction First Mesurements ECCTD07","year":"2007","author":"ferna?ndez-garci?a","key":"2"},{"key":"10","first-page":"77","author":"saegusa","year":"2008","journal-title":"How Fast is an FPGA in Image Processing? FPL08"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/81.222795"},{"journal-title":"Stratix Programmable Logic Device Family Data Sheet","year":"2002","key":"7"},{"journal-title":"Single Instruction Multiple Data and Cellular Non-linear Networks as Fine-Grained Parallel Solutions for Early Vision on FPGAs DCIS08","year":"2008","author":"nieto","key":"6"},{"journal-title":"Discrete Time Cellular Non-linear Networks Implementation over FPGA DCIS08","year":"2008","author":"albo?-canals","key":"5"},{"journal-title":"Template-Oriented Hardware Design based on Shape Analysis of 2D CNN Operators in CNN Template Libraries and Applications CNNA08","year":"2008","author":"ferna?ndez-garci?a","key":"4"},{"journal-title":"Configurable multi-layer CNN-UM emulator on FPGA using Distributed Arithmetic ICECS02","year":"2002","author":"nagy","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1002\/cta.212"}],"event":{"name":"2009 European Conference on Circuit Theory and Design (ECCTD 2009)","start":{"date-parts":[[2009,8,23]]},"location":"Antalya, Turkey","end":{"date-parts":[[2009,8,27]]}},"container-title":["2009 European Conference on Circuit Theory and Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5247537\/5274921\/05275114.pdf?arnumber=5275114","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,17]],"date-time":"2021-06-17T20:08:45Z","timestamp":1623960525000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5275114\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,8]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ecctd.2009.5275114","relation":{},"subject":[],"published":{"date-parts":[[2009,8]]}}}