{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:49:45Z","timestamp":1759146585011},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,8]]},"DOI":"10.1109\/ecctd.2011.6043407","type":"proceedings-article","created":{"date-parts":[[2011,10,13]],"date-time":"2011-10-13T16:55:12Z","timestamp":1318524912000},"page":"536-539","source":"Crossref","is-referenced-by-count":14,"title":["Impact of NMOS\/PMOS imbalance in Ultra-Low Voltage CMOS standard cells"],"prefix":"10.1109","author":[{"given":"Massimo","family":"Alioto","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2034233"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837945"},{"article-title":"MOSFET Modeling & BSIM3 User's Guide","year":"1999","author":"cheng","key":"ref6"},{"key":"ref5","article-title":"Ultra-Low Power VLSI Design Demystified and Explained: a Tutorial","author":"alioto","year":"0","journal-title":"print on IEEE Trans on Circuits and Systems - part I (invited extended paper)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917505"},{"article-title":"Operation and Modeling of the MOS Transistor","year":"1999","author":"tsividis","key":"ref7"},{"key":"ref2","article-title":"Ultra-low-power design - the Roadmap to disappearing electronics and ambient intelligence","author":"rabaey","year":"2006","journal-title":"IEEE Circuits & Devices Magazine"},{"key":"ref9","first-page":"127","article-title":"Utilizing reverse short channel effect for optimal subthreshold circuit design","author":"kim","year":"2006","journal-title":"Proc &#x201D; of ISLPED 2006"},{"key":"ref1","article-title":"Increasing Minimum Operating Voltage (VDDmin) with Number of CMOS Logic Gates and Experimental Verification with up to IMega-Stage Ring Oscillators","author":"sakurai","year":"2008","journal-title":"Proc of ISLPED"}],"event":{"name":"2011 European Conference on Circuit Theory and Design (ECCTD)","start":{"date-parts":[[2011,8,29]]},"location":"Linkoping, Sweden","end":{"date-parts":[[2011,8,31]]}},"container-title":["2011 20th European Conference on Circuit Theory and Design (ECCTD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6033674\/6043284\/06043407.pdf?arnumber=6043407","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,20]],"date-time":"2017-03-20T22:50:34Z","timestamp":1490050234000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6043407\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/ecctd.2011.6043407","relation":{},"subject":[],"published":{"date-parts":[[2011,8]]}}}