{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:37:03Z","timestamp":1729661823039,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,8]]},"DOI":"10.1109\/ecctd.2011.6043603","type":"proceedings-article","created":{"date-parts":[[2011,10,13]],"date-time":"2011-10-13T16:55:12Z","timestamp":1318524912000},"page":"592-595","source":"Crossref","is-referenced-by-count":0,"title":["Optimization and evaluation of tapered-V&lt;inf&gt;TH&lt;\/inf&gt; approach for energy-efficient CMOS buffers"],"prefix":"10.1109","author":[{"given":"Fabio","family":"Frustaci","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pasquale","family":"Corsonello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Massimo","family":"Alioto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938006"},{"year":"1999","key":"ref11","article-title":"Logical Effort: Designing Fast CMOS Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2033538"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.906983"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270271"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.109565"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/92.365457"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.84943"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TVLSI.2008.2003169","article-title":"Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy\/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning","volume":"17","author":"wang","year":"2009","journal-title":"IEEE Trans on VLSI Systems"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.309912"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.58293"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.907784"}],"event":{"name":"2011 European Conference on Circuit Theory and Design (ECCTD)","start":{"date-parts":[[2011,8,29]]},"location":"Linkoping, Sweden","end":{"date-parts":[[2011,8,31]]}},"container-title":["2011 20th European Conference on Circuit Theory and Design (ECCTD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6033674\/6043284\/06043603.pdf?arnumber=6043603","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T03:55:33Z","timestamp":1497930933000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6043603\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ecctd.2011.6043603","relation":{},"subject":[],"published":{"date-parts":[[2011,8]]}}}