{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T13:33:14Z","timestamp":1725456794200},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,9]]},"DOI":"10.1109\/esscirc.2009.5326010","type":"proceedings-article","created":{"date-parts":[[2009,11,18]],"date-time":"2009-11-18T19:39:49Z","timestamp":1258573189000},"page":"156-159","source":"Crossref","is-referenced-by-count":5,"title":["647 MHz, 0.642pJ\/block\/cycle 65nm self synchronous FPGA"],"prefix":"10.1109","author":[{"given":"Benjamin","family":"Devlin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeong","family":"MyeongGyu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toru","family":"Nakura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Makoto","family":"Ikeda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kunihiro","family":"Asada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"3"},{"key":"2","article-title":"Implementing Asynchronous Circuits on LUT Based FPGAs","author":"ho","year":"2002","journal-title":"Proc Intl Conf Field Programmable Logic and Appl"},{"year":"0","key":"10"},{"journal-title":"ITRS 2007 Report","article-title":"Online]. Available","year":"0","key":"1"},{"key":"7","article-title":"Moebius Circuit: Dual-Rail Dynamic Logic for Logic Gate Level Pipeline with Error Gate Search Feature","author":"myeonggyu","year":"2009","journal-title":"VLSI 2009 Proceedings Nineteenth Great Lakes Symposium on"},{"year":"0","key":"6"},{"year":"0","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.88"},{"key":"9","article-title":"Which is the best dual-port SRAM in 45-nm process technology? 8T, 10T single end, and 10T differential","author":"noguchi","year":"2008","journal-title":"Integrated Circuit Design and Technology and Tutorial"},{"year":"0","key":"8"}],"event":{"name":"2009 Proceedings of ESSCIRC (ESSCIRC)","start":{"date-parts":[[2009,9,14]]},"location":"Athens, Greece","end":{"date-parts":[[2009,9,18]]}},"container-title":["2009 Proceedings of ESSCIRC"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5307451\/5325915\/05326010.pdf?arnumber=5326010","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T13:48:15Z","timestamp":1489758495000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5326010\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2009.5326010","relation":{},"subject":[],"published":{"date-parts":[[2009,9]]}}}