{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T00:05:16Z","timestamp":1725667516924},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,9]]},"DOI":"10.1109\/esscirc.2009.5326028","type":"proceedings-article","created":{"date-parts":[[2009,11,19]],"date-time":"2009-11-19T00:39:49Z","timestamp":1258591189000},"page":"340-343","source":"Crossref","is-referenced-by-count":5,"title":["Power reduction techniques for an 8-core xeon<sup>®<\/sup> processor"],"prefix":"10.1109","author":[{"given":"Stefan","family":"Rusu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simon","family":"Tam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Harry","family":"Muljono","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Stinson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Ayers","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jonathan","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raj","family":"Varada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matt","family":"Ratta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sailesh","family":"Kottapalli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sujal","family":"Vora","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-K Metal-Gate CMOS Technology","author":"hamzaoglu","year":"2008","journal-title":"ISSCCDig Tech"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977305"},{"key":"1","article-title":"A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging","author":"mistry","year":"2007","journal-title":"IEDM Tech"},{"key":"4","article-title":"Nehalem: A family of 45 nm IA processors","author":"kumar","year":"2009","journal-title":"ISSCCDig Tech"}],"event":{"name":"2009 Proceedings of ESSCIRC (ESSCIRC)","start":{"date-parts":[[2009,9,14]]},"location":"Athens, Greece","end":{"date-parts":[[2009,9,18]]}},"container-title":["2009 Proceedings of ESSCIRC"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5307451\/5325915\/05326028.pdf?arnumber=5326028","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T23:37:13Z","timestamp":1489880233000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5326028\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,9]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2009.5326028","relation":{},"subject":[],"published":{"date-parts":[[2009,9]]}}}