{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T01:38:11Z","timestamp":1725500291844},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,9]]},"DOI":"10.1109\/esscirc.2012.6341287","type":"proceedings-article","created":{"date-parts":[[2012,11,15]],"date-time":"2012-11-15T17:07:41Z","timestamp":1352999261000},"page":"177-180","source":"Crossref","is-referenced-by-count":0,"title":["A 260mV 468GOPS\/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS"],"prefix":"10.1109","author":[{"given":"Amit","family":"Agarwal","sequence":"first","affiliation":[]},{"given":"Steven","family":"Hsu","sequence":"additional","affiliation":[]},{"given":"Sanu","family":"Mathew","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Anders","sequence":"additional","affiliation":[]},{"given":"Himanshu","family":"Kaul","sequence":"additional","affiliation":[]},{"given":"Farhana","family":"Sheikh","sequence":"additional","affiliation":[]},{"given":"Ram","family":"Krishnamurthy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"264","article-title":"A fully integrated multi-CPU, GPU and memory controller 32nm processor","author":"yuffe","year":"2011","journal-title":"IEEE ISSCC Digest Tech Papers"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523182"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169689"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176966"},{"key":"6","first-page":"230","article-title":"A 4.6GHz 162mb SRAM design in 22nm Tr-Gate CMOS technology with integrated active Vminenhancing assist circuitry","author":"karl","year":"2012","journal-title":"IEEE ISSCC Digest Tech Papers"},{"key":"5","first-page":"394","article-title":"A mixed signal rotator\/shifter for 8 GHz Intel Pentium 4 integer core","author":"singh","year":"2004","journal-title":"Symposium on VLSI Circuits"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2006.355049"}],"event":{"name":"ESSCIRC 2012 - 38th European Solid State Circuits Conference","start":{"date-parts":[[2012,9,17]]},"location":"Bordeaux, France","end":{"date-parts":[[2012,9,21]]}},"container-title":["2012 Proceedings of the ESSCIRC (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6331297\/6341242\/06341287.pdf?arnumber=6341287","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T20:09:08Z","timestamp":1490126948000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6341287\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2012.6341287","relation":{},"subject":[],"published":{"date-parts":[[2012,9]]}}}