{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T17:05:29Z","timestamp":1769015129231,"version":"3.49.0"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/esscirc.2015.7313884","type":"proceedings-article","created":{"date-parts":[[2015,11,2]],"date-time":"2015-11-02T23:13:57Z","timestamp":1446506037000},"page":"291-294","source":"Crossref","is-referenced-by-count":7,"title":["120V\/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs"],"prefix":"10.1109","author":[{"given":"Hsiang-An","family":"Yang","sequence":"first","affiliation":[]},{"given":"Chao-Chang","family":"Chiu","sequence":"additional","affiliation":[]},{"given":"Shin-Chi","family":"Lai","sequence":"additional","affiliation":[]},{"given":"Jui-Lung","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Chih-Wei","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Che-Hao","family":"Meng","sequence":"additional","affiliation":[]},{"given":"Ke-Horng","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Chin-Long","family":"Wey","sequence":"additional","affiliation":[]},{"given":"Ying-Hsi","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Chao-Cheng","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jian-Ru","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Tsung-Yen","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Hsin-Yu","family":"Luo","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.923734"},{"key":"ref3","first-page":"891","article-title":"High-voltage power IC technology with nVDMOS, RESURF pLDMOS, and novel level-shift circuit for PDP scan-driver IC","author":"sun","year":"2006","journal-title":"IEEE Tran Electron Devices"},{"key":"ref5","article-title":"LM5113 5A, 100V half-bridge gate driver for enhancement mode GaN FETs","year":"2013"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2225736"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2263578"}],"event":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference","location":"Graz, Austria","start":{"date-parts":[[2015,9,14]]},"end":{"date-parts":[[2015,9,18]]}},"container-title":["ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7300343\/7313811\/07313884.pdf?arnumber=7313884","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T05:02:25Z","timestamp":1490418145000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7313884\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2015.7313884","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}