{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T16:44:23Z","timestamp":1730220263271,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/esscirc.2015.7313906","type":"proceedings-article","created":{"date-parts":[[2015,11,2]],"date-time":"2015-11-02T18:13:57Z","timestamp":1446488037000},"page":"376-379","source":"Crossref","is-referenced-by-count":3,"title":["A 28.5&amp;#x2013;33.5GHz fractional-N PLL using a 3&lt;sup&gt;rd&lt;\/sup&gt; order noise shaping time-to-digital converter with 176fs resolution"],"prefix":"10.1109","author":[{"given":"Mehmet Batuhan","family":"Dayanik","sequence":"first","affiliation":[]},{"given":"Nicholas","family":"Collins","sequence":"additional","affiliation":[]},{"given":"Michael P.","family":"Flynn","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"A low-noise, wide-BW 3.6GHz digital $\\Delta\\Sigma$ frac-N frequency synthesizer with noise-shaping TDC and quantizations noise cancellation","author":"hsu","year":"2008","journal-title":"ISSCC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617612"},{"key":"ref12","article-title":"A 13.1-to-28GHz Fractional-NPLL in 32nm SOI CMOS with a $\\sum\\Delta$ Noise Cancellation Scheme","author":"ferriss","year":"2015","journal-title":"ISSCC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977324"},{"key":"ref4","article-title":"A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS","author":"wu","year":"2013","journal-title":"ISSCC"},{"key":"ref3","article-title":"A 13b 315fsrms 2mW 500MS\/s 1MHz BW highly digital time-to-digital converter using switched ring oscillators","author":"elshazly","year":"2012","journal-title":"ISSCC"},{"key":"ref6","article-title":"A 2.5Gb\/s multi-rate 0.25um CMOS CDR utilizing a hybrid analog\/digital loop filter","author":"perrott","year":"2006","journal-title":"ISSCC"},{"key":"ref5","article-title":"A 28GHz hybrid PLL in 32nm SOI CMOS","author":"ferriss","year":"2013","journal-title":"VLSI Symposium"},{"key":"ref8","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE TCAS II"},{"key":"ref7","article-title":"A 21.8&#x2013;27.5GHz PLL in 32nm SOI using Gm linearization to achieve ?130dBc\/Hz phase noise at 10MHz offset from 22GHz carrier","author":"sadhu","year":"2012","journal-title":"RFIC"},{"key":"ref2","article-title":"A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS","author":"yi","year":"2013","journal-title":"ISSCC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757472"},{"key":"ref9","article-title":"A 1.7mW 11b 1-1-1 MASH $\\Delta\\Sigma$ time-to-digital converter","author":"cao","year":"2011","journal-title":"ISSCC"}],"event":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference","start":{"date-parts":[[2015,9,14]]},"location":"Graz, Austria","end":{"date-parts":[[2015,9,18]]}},"container-title":["ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7300343\/7313811\/07313906.pdf?arnumber=7313906","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T01:26:54Z","timestamp":1490405214000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7313906\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2015.7313906","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}