{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:58:50Z","timestamp":1761663530104,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/esscirc.2016.7598278","type":"proceedings-article","created":{"date-parts":[[2016,10,20]],"date-time":"2016-10-20T17:07:39Z","timestamp":1476983259000},"page":"205-208","source":"Crossref","is-referenced-by-count":9,"title":["A 2 GHz 3.1 mW type-I digital ring-based PLL"],"prefix":"10.1109","author":[{"given":"Zule","family":"Xu","sequence":"first","affiliation":[]},{"given":"Anugerah","family":"Firdauzi","sequence":"additional","affiliation":[]},{"given":"Masaya","family":"Miyahara","sequence":"additional","affiliation":[]},{"given":"Kenichi","family":"Okada","sequence":"additional","affiliation":[]},{"given":"Akira","family":"Matsuzawa","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"440","article-title":"A 2.2GHz ?242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture","volume":"58","author":"siriburanon","year":"0"},{"key":"ref3","first-page":"336","article-title":"A 65nm CMOS ADPLL with 360?W 1.6ps-INL SS-ADC-based period-detection-free TDC","author":"sai","year":"2016","journal-title":"IEEE ISSCC"},{"key":"ref10","first-page":"253","article-title":"A Ring-VCO-Based Sub-Sampling PLL CMOS Circuit with ?119 dBc\/Hz Phase Noise and 0. 73 ps Jitter","volume":"2","author":"sogo","year":"2012","journal-title":"IEEE ESSCIRC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417963"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385756"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"821","DOI":"10.1109\/JSSC.2016.2519391","article-title":"A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques","volume":"51","author":"kuan","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658465"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757430"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063120"}],"event":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","start":{"date-parts":[[2016,9,12]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2016,9,15]]}},"container-title":["ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7585490\/7598228\/07598278.pdf?arnumber=7598278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T21:44:18Z","timestamp":1498340658000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7598278\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2016.7598278","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}