{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,13]],"date-time":"2025-09-13T15:38:03Z","timestamp":1757777883933},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/esscirc.2016.7598333","type":"proceedings-article","created":{"date-parts":[[2016,10,20]],"date-time":"2016-10-20T17:07:39Z","timestamp":1476983259000},"page":"429-432","source":"Crossref","is-referenced-by-count":4,"title":["A 128 kb single-bitline 8.4 fJ\/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI"],"prefix":"10.1109","author":[{"given":"Babak","family":"Mohammadi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oskar","family":"Andersson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph","family":"Nguyen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lorenzo","family":"Ciampolini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreia","family":"Cathelin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joachim Neves","family":"Rodrigues","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"FDSOI process\/design full solutions for ultra low leakage, high speed and low voltage SRAMs","author":"ranica","year":"2013","journal-title":"Symp on VLSI Technology"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6861178"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.872704"},{"key":"ref13","first-page":"264","article-title":"Capacitive-Coupling Wordline Boosting with Self-Induced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM","author":"khellah","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf"},{"key":"ref14","first-page":"254","article-title":"14nm FinFET Based Supply Voltage Boosting Techniques for Extreme Low Vmin Operation","author":"joshi","year":"2015","journal-title":"Symp on VLSI Technology"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548579"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2316219"},{"key":"ref17","first-page":"337","article-title":"A 300mV Sub-1pJ differential 6T sub-threshold SRAM with low energy and variability resilient local assist circuit","author":"chiou","year":"2013","journal-title":"Int Symp on Next Generation Electronics"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746310"},{"key":"ref4","first-page":"130","article-title":"A 210mV 7.3MHz 8T SRAM with Dual Data-Aware Write-Assists and Negative Read Wordline for High Cell-Stability, Speed and Area-Efficiency","author":"chen","year":"2013","journal-title":"Symp on VLSI Circuits"},{"key":"ref3","first-page":"72","article-title":"A 40-nm 0.5-V 20.1-uW MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme","author":"yoshimoto","year":"2011","journal-title":"Symp on VLSI CIRCUIT"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164009"},{"key":"ref5","first-page":"252","article-title":"A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS","author":"chang","year":"2007","journal-title":"IEEE Symp on VLSI Circuits"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280733"},{"key":"ref7","first-page":"306","article-title":"A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance, and Area Optimization","author":"taejoong","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433815"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2012.6329064"}],"event":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","start":{"date-parts":[[2016,9,12]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2016,9,15]]}},"container-title":["ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7585490\/7598228\/07598333.pdf?arnumber=7598333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,11,2]],"date-time":"2016-11-02T03:09:04Z","timestamp":1478056144000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7598333\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2016.7598333","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}