{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:53:05Z","timestamp":1729615985428,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/esscirc.2016.7598345","type":"proceedings-article","created":{"date-parts":[[2016,10,20]],"date-time":"2016-10-20T21:07:39Z","timestamp":1476997659000},"page":"477-482","source":"Crossref","is-referenced-by-count":1,"title":["Design considerations for 50G+ backplane links"],"prefix":"10.1109","author":[{"given":"Thomas","family":"Toifl","sequence":"first","affiliation":[]},{"given":"Matthias","family":"Brandli","sequence":"additional","affiliation":[]},{"given":"Alessandro","family":"Cevrero","sequence":"additional","affiliation":[]},{"given":"Pier Andrea","family":"Francese","sequence":"additional","affiliation":[]},{"given":"Marcel","family":"Kossel","sequence":"additional","affiliation":[]},{"given":"Lukas","family":"Kull","sequence":"additional","affiliation":[]},{"given":"Danny","family":"Luu","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Menolfi","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Morf","sequence":"additional","affiliation":[]},{"given":"Ilter","family":"Ozkaya","sequence":"additional","affiliation":[]},{"given":"Hazar","family":"Yueksel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Novel FEXT Cancellation and Equalization for High Speed Ethernet Transmission","volume":"56","author":"chen","year":"2009","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071431"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1109\/ASSCC.2014.7008867","article-title":"A 110 mW 6 bit 36 GS\/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS","author":"kull","year":"2014","journal-title":"IEEE Asian Solid-State Circuits Conference (A-SSCC)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref14","article-title":"A 3.6 pJ\/b 56 Gb\/s 4-PAM Receiver With 6-Bit TI-SAR ADC and Quarter-Rate Speculative 2-Tap DFE in 32 nm CMOS","author":"yueksel","year":"0","journal-title":"European Solid State Circuits Conference (ESSCIRC) 2015"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942120"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417904"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2013.6685768"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.585246"},{"journal-title":"A 4 1 pJ\/b 25 6 Gb\/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS","year":"0","author":"yueksel","key":"ref19"},{"year":"0","author":"mellitz","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216414"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487622"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185342"},{"journal-title":"$4\\times 12$ Gb\/s 0 96 pJ\/b\/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I\/Os in 65 nm CMOS","year":"2012","author":"oh","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942115"},{"key":"ref2","article-title":"ISI Tolerant Signaling: A Comparative Study of PAM4 and ENRZ","author":"hormati","year":"2016","journal-title":"DesignCon 2016"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2010.5594694"},{"key":"ref9","article-title":"A 5.9mW\/Gb\/s 56Gb\/s 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS","author":"cevrero","year":"2015","journal-title":"IEEE Symposium on VLSI Circuits"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1982.1056454"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.904688"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279057"}],"event":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","start":{"date-parts":[[2016,9,12]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2016,9,15]]}},"container-title":["ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7585490\/7598228\/07598345.pdf?arnumber=7598345","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,10]],"date-time":"2022-07-10T21:53:29Z","timestamp":1657490009000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7598345\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2016.7598345","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}