{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T09:59:47Z","timestamp":1771667987121,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/esscirc.2017.8094523","type":"proceedings-article","created":{"date-parts":[[2017,11,28]],"date-time":"2017-11-28T16:03:53Z","timestamp":1511885033000},"page":"51-54","source":"Crossref","is-referenced-by-count":13,"title":["Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering"],"prefix":"10.1109","author":[{"given":"Arvind","family":"Singh","sequence":"first","affiliation":[]},{"given":"Monodeep","family":"Kar","sequence":"additional","affiliation":[]},{"given":"Sanu","family":"Mathew","sequence":"additional","affiliation":[]},{"given":"Anand","family":"Rajan","sequence":"additional","affiliation":[]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[]},{"given":"Saibal","family":"Mukhopadhyay","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598339"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231033"},{"key":"ref12","author":"goodwil","year":"0","journal-title":"NIST Technical Report"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2505261"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2015.7273503"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495573"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934607"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870301"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977309"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231274"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859886"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2012.16"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744866"},{"key":"ref1","article-title":"Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach","author":"yang","year":"0","journal-title":"DATE'05"},{"key":"ref9","article-title":"FIVR - Fully Integrated Voltage Regulators on 4th Generation Intel&#x00AE; Core&#x2122; SoCs","author":"burton","year":"0","journal-title":"APEC'14"}],"event":{"name":"ESSCIRC 2017 - 43rd IEEE European Solid-State Circuits Conference","location":"Leuven","start":{"date-parts":[[2017,9,11]]},"end":{"date-parts":[[2017,9,14]]}},"container-title":["ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8061155\/8094509\/08094523.pdf?arnumber=8094523","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,11]],"date-time":"2017-12-11T22:38:39Z","timestamp":1513031919000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8094523\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2017.8094523","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}