{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T16:32:03Z","timestamp":1725553923739},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/esscirc.2017.8094539","type":"proceedings-article","created":{"date-parts":[[2017,11,28]],"date-time":"2017-11-28T16:03:53Z","timestamp":1511885033000},"page":"115-118","source":"Crossref","is-referenced-by-count":1,"title":["DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology"],"prefix":"10.1109","author":[{"given":"Marcel","family":"Kossel","sequence":"first","affiliation":[]},{"given":"Christian","family":"Menolfi","sequence":"additional","affiliation":[]},{"given":"Pier Andrea","family":"Francese","sequence":"additional","affiliation":[]},{"given":"Lukas","family":"Kull","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Morf","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Toifl","sequence":"additional","affiliation":[]},{"given":"Matthias","family":"Brandli","sequence":"additional","affiliation":[]},{"given":"Alessandro","family":"Cevrero","sequence":"additional","affiliation":[]},{"given":"Danny","family":"Luu","sequence":"additional","affiliation":[]},{"given":"Ilter","family":"Ozkaya","sequence":"additional","affiliation":[]},{"given":"Hazar","family":"Yueksel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"136","article-title":"Single-ended transceiver design techniques for 5.33 Gb\/s graphics applications","author":"partovi","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"135","article-title":"A DDR3\/4 memory link TX supporting 24–40 ?, 0.8–1.6V, 0.8-5.0 Gb\/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI","author":"kossel","year":"2014","journal-title":"Proc ESSCIRC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2009.5423864"},{"key":"ref2","first-page":"50","article-title":"POWER9TM: A processor family optimized for cognitive computing with 25Gb\/s accelerator links and 16Gb\/s PCIe Gen4","author":"gonzalez","year":"2017","journal-title":"ISSCC Dig Tech Papers"},{"journal-title":"JEDEC JESD79–4B","article-title":"DDR4 SDRAM Standard","year":"2016","key":"ref1"}],"event":{"name":"ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference (ESSCIRC)","start":{"date-parts":[[2017,9,11]]},"location":"Leuven, Belgium","end":{"date-parts":[[2017,9,14]]}},"container-title":["ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8061155\/8094509\/08094539.pdf?arnumber=8094539","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,11,30]],"date-time":"2017-11-30T20:06:05Z","timestamp":1512072365000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8094539\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2017.8094539","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}