{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T13:05:25Z","timestamp":1762607125472},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/esscirc.2017.8094575","type":"proceedings-article","created":{"date-parts":[[2017,11,28]],"date-time":"2017-11-28T11:03:53Z","timestamp":1511867033000},"page":"259-262","source":"Crossref","is-referenced-by-count":22,"title":["OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators"],"prefix":"10.1109","author":[{"given":"Chixiao","family":"Chen","sequence":"first","affiliation":[]},{"given":"Hongwei","family":"Ding","sequence":"additional","affiliation":[]},{"given":"Huwan","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Haozhe","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"Rui","family":"Ma","sequence":"additional","affiliation":[]},{"given":"Peiyong","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Xiaolang","family":"Yan","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Mingyu","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Hao","family":"Min","sequence":"additional","affiliation":[]},{"given":"Richard C.-J","family":"Shi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870350"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573525"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.8.1735"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/5326.983933"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3115\/v1\/P15-1150"},{"key":"ref7","article-title":"Empirical Evaluation of Gated Recurrent Neural Networks on Sequence Modeling","author":"cho","year":"2015","journal-title":"ICML"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418008"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"}],"event":{"name":"ESSCIRC 2017 - 43rd IEEE European Solid-State Circuits Conference","start":{"date-parts":[[2017,9,11]]},"location":"Leuven","end":{"date-parts":[[2017,9,14]]}},"container-title":["ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8061155\/8094509\/08094575.pdf?arnumber=8094575","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T14:21:34Z","timestamp":1513174894000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8094575\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2017.8094575","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}