{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T13:37:08Z","timestamp":1725457028582},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/esscirc.2018.8494253","type":"proceedings-article","created":{"date-parts":[[2018,12,7]],"date-time":"2018-12-07T16:18:18Z","timestamp":1544199498000},"page":"22-25","source":"Crossref","is-referenced-by-count":2,"title":["A 125 MS\/s 10.4 ENOB 10.1 fJ\/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS"],"prefix":"10.1109","author":[{"given":"Shaolong","family":"Liu","sequence":"first","affiliation":[]},{"given":"Jeyanandh","family":"Paramesh","sequence":"additional","affiliation":[]},{"given":"Larry","family":"Pileggi","sequence":"additional","affiliation":[]},{"given":"Taimur","family":"Rabuske","sequence":"additional","affiliation":[]},{"given":"Jorge","family":"Fernandcs","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598330"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2723799"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2417803"},{"key":"ref13","article-title":"A 46 &#x00B5;W 13b 6.4 MS\/s SAR ADC with background mismatch and offset calibration","author":"ding","year":"2017","journal-title":"IEEE JSSC"},{"key":"ref4","article-title":"A 70dB SNDR 200MS\/s 2.3mW dynamic pipelined SAR ADC in 28nm digital CMOS","author":"verbruggen","year":"2014","journal-title":"IEEE VLSI Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008562"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008559"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.917991"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2379613"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008506"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231328"},{"key":"ref9","article-title":"A 3.1mW 8b 1.2 GS\/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS","author":"kull","year":"2013","journal-title":"IEEE JSSC"}],"event":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","start":{"date-parts":[[2018,9,3]]},"location":"Dresden","end":{"date-parts":[[2018,9,6]]}},"container-title":["ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8476980\/8494227\/08494253.pdf?arnumber=8494253","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T22:36:42Z","timestamp":1598222202000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8494253\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2018.8494253","relation":{},"subject":[],"published":{"date-parts":[[2018,9]]}}}