{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:06:13Z","timestamp":1767182773531},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1109\/esscirc.2019.8902909","type":"proceedings-article","created":{"date-parts":[[2019,11,25]],"date-time":"2019-11-25T19:29:08Z","timestamp":1574710148000},"page":"241-244","source":"Crossref","is-referenced-by-count":8,"title":["Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN)"],"prefix":"10.1109","author":[{"given":"Yun-Chen","family":"Lo","sequence":"first","affiliation":[]},{"given":"Yu-Chun","family":"Kuo","sequence":"additional","affiliation":[]},{"given":"Yun-Sheng","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Jian-Hao","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Jun-Shen","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Wen-Chien","family":"Ting","sequence":"additional","affiliation":[]},{"given":"Tai-Hsing","family":"Wen","sequence":"additional","affiliation":[]},{"given":"Ren-Shuo","family":"Liu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Considerations of integrating computing-in-memory and processing-in-sensor into convolutional neural network accelerators for low-power edge devices","author":"tang","year":"2019","journal-title":"VLSI"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2018.8494245"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001179"},{"key":"ref13","article-title":"XNOR-Net: ImageNet classification using binary convolutional neural networks","author":"rastegari","year":"2016","journal-title":"ECCV"},{"key":"ref14","article-title":"SCRx family of the RISC-V compatible core IP by Syntacore","author":"redkin","year":"2019","journal-title":"RisC- V Workshop"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310400"},{"key":"ref16","article-title":"A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning","author":"si","year":"2019","journal-title":"ISSCC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502388"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021741"},{"journal-title":"SiFive FE (FE310) Chip Disigner","year":"0","key":"ref4"},{"year":"0","key":"ref3","article-title":"MediaTek MT2523 werable chipset and MT7687 smart home chipset"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref5","article-title":"A 1Mb multibit ReRAM computing-in-memory macro with 14.6ns parallel MAC computing time for CNN based AI edge processors","author":"xue","year":"2019","journal-title":"ISSCC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2015.123"},{"article-title":"BinaryNet: Training deep neural networks with weights and activations constrained to +1 or -1","year":"2016","author":"courbariaux","key":"ref7"},{"year":"0","key":"ref2","article-title":"Deep learning extension for VectorBlox ORCA RISC-V processors"},{"year":"0","key":"ref1","article-title":"AndesCore N25 and NX25 RISC-V processors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00745"}],"event":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","start":{"date-parts":[[2019,9,23]]},"location":"Cracow, Poland","end":{"date-parts":[[2019,9,26]]}},"container-title":["ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8895615\/8902346\/08902909.pdf?arnumber=8902909","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:09:34Z","timestamp":1657854574000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8902909\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/esscirc.2019.8902909","relation":{},"subject":[],"published":{"date-parts":[[2019,9]]}}}