{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:11:58Z","timestamp":1740100318441,"version":"3.37.3"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,13]],"date-time":"2021-09-13T00:00:00Z","timestamp":1631491200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,13]],"date-time":"2021-09-13T00:00:00Z","timestamp":1631491200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,13]],"date-time":"2021-09-13T00:00:00Z","timestamp":1631491200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100007225","name":"MOST","doi-asserted-by":"publisher","award":["106-2221-E-002-238"],"award-info":[{"award-number":["106-2221-E-002-238"]}],"id":[{"id":"10.13039\/100007225","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,13]]},"DOI":"10.1109\/esscirc53450.2021.9567756","type":"proceedings-article","created":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T21:10:54Z","timestamp":1635282654000},"page":"107-110","source":"Crossref","is-referenced-by-count":1,"title":["A 1.625 TOPS\/W SOC for Deep CNN Training and Inference in 28nm CMOS"],"prefix":"10.1109","author":[{"given":"Yu-Tung","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"ChuKing","family":"Kung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming-Hang","family":"Hsieh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hsiu-Wen","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun-Pin","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chao-Yang","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chi-Shi","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tzi-Dar","family":"Chiueh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"107","article-title":"F-CNN: An FPGA-based Framework for Training Convolutional Neural Networks","author":"zhao","year":"2016","journal-title":"Proc of 2016 IEEE 27th International Conference on Application-specific Systems Architectures and Processors (ASAP)"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/JSSC.2018.2865489"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/A-SSCC47793.2019.9056967"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ISSCC.2019.8662302"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/JSSC.2020.3005786"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ICCD.2016.7753296"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/JETCAS.2019.2911999"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/VLSIC.2018.8502276"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/VLSIC.2018.8502404"},{"key":"ref9","first-page":"7685","article-title":"Training Deep Neural Networks with 8-bit Floating Point Numbers","author":"wang","year":"0","journal-title":"Proc of Adv Neural Inf Process Syst"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/JSSC.2016.2616357"}],"event":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","start":{"date-parts":[[2021,9,13]]},"location":"Grenoble, France","end":{"date-parts":[[2021,9,22]]}},"container-title":["ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9567713\/9567736\/09567756.pdf?arnumber=9567756","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:53:21Z","timestamp":1652201601000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9567756\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,13]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/esscirc53450.2021.9567756","relation":{},"subject":[],"published":{"date-parts":[[2021,9,13]]}}}