{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T17:08:26Z","timestamp":1773248906591,"version":"3.50.1"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,13]],"date-time":"2021-09-13T00:00:00Z","timestamp":1631491200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,13]],"date-time":"2021-09-13T00:00:00Z","timestamp":1631491200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,13]]},"DOI":"10.1109\/esscirc53450.2021.9567844","type":"proceedings-article","created":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T21:10:54Z","timestamp":1635282654000},"page":"79-82","source":"Crossref","is-referenced-by-count":13,"title":["A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References"],"prefix":"10.1109","author":[{"given":"Wantong","family":"Li","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology,Atlanta,GA,USA,30332"}]},{"given":"Xiaoyu","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology,Atlanta,GA,USA,30332"}]},{"given":"Hongwu","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology,Atlanta,GA,USA,30332"}]},{"given":"Shanshi","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology,Atlanta,GA,USA,30332"}]},{"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology,Atlanta,GA,USA,30332"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Secure-RRAM: A 40nm 16kb compute-in-memory macro with reconfigurability, sparsity control, and embedded security","author":"li","year":"0","journal-title":"IEEE Custom Integrated Circuits Conference (CICC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3010795"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9181022"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310392"},{"key":"ref2","article-title":"A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7TOPS\/W for tiny AI edge devices","author":"xue","year":"0","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"ref1","article-title":"High-density 3D monolithically integrated multiple 1T1R multi-level-cell for neural networks","author":"esmanhotto","year":"0","journal-title":"IEEE International Electron Devices Meeting (IEDM)"}],"event":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","location":"Grenoble, France","start":{"date-parts":[[2021,9,13]]},"end":{"date-parts":[[2021,9,22]]}},"container-title":["ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9567713\/9567736\/09567844.pdf?arnumber=9567844","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,2]],"date-time":"2022-08-02T23:38:50Z","timestamp":1659483530000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9567844\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,13]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/esscirc53450.2021.9567844","relation":{},"subject":[],"published":{"date-parts":[[2021,9,13]]}}}