{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,14]],"date-time":"2026-02-14T02:34:28Z","timestamp":1771036468176,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,9,19]],"date-time":"2022-09-19T00:00:00Z","timestamp":1663545600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,9,19]],"date-time":"2022-09-19T00:00:00Z","timestamp":1663545600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,9,19]]},"DOI":"10.1109\/esscirc55480.2022.9911359","type":"proceedings-article","created":{"date-parts":[[2022,11,3]],"date-time":"2022-11-03T21:58:34Z","timestamp":1667512714000},"page":"89-92","source":"Crossref","is-referenced-by-count":2,"title":["A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation\/Weight Sparsification"],"prefix":"10.1109","author":[{"given":"Shreyas Kolala","family":"Venkataramanaiah","sequence":"first","affiliation":[{"name":"Arizona State University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jian","family":"Meng","sequence":"additional","affiliation":[{"name":"Arizona State University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Han-Sok","family":"Suh","sequence":"additional","affiliation":[{"name":"Arizona State University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Injune","family":"Yeo","sequence":"additional","affiliation":[{"name":"Arizona State University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jyotishman","family":"Saikia","sequence":"additional","affiliation":[{"name":"Arizona State University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sai Kiran","family":"Cherupally","sequence":"additional","affiliation":[{"name":"Arizona State University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yichi","family":"Zhang","sequence":"additional","affiliation":[{"name":"Cornell University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"Cornell University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae-sun","family":"Seo","sequence":"additional","affiliation":[{"name":"Arizona State University,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218650"},{"key":"ref7","article-title":"Channel gating neural networks","author":"hua","year":"2019","journal-title":"NeurIPS"},{"key":"ref9","article-title":"A simple framework for contrastive learning of visual representations","author":"chen","year":"2020","journal-title":"ICML"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSICircuits18222.2020.9162795"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3066400"},{"key":"ref6","article-title":"Learning structured sparsity in deep neural networks","author":"wen","year":"2016","journal-title":"NeurIPS"},{"key":"ref5","article-title":"A 28nm 276.55 TFLOPS\/W sparse deep-neural-network training processor with implicit redundancy speculation and batch nor-malization reformulation","author":"wang","year":"0","journal-title":"Symp on VLSI Circuits"},{"key":"ref2","article-title":"A 40nm 4.81 TFLOPS\/W 8b floating-point training processor for non-sparse neural networks using shared exponent bias and 24-Way fused multiply-add tree","author":"park","year":"2021","journal-title":"IEEE ISSCC"},{"key":"ref1","article-title":"A 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling","author":"agrawal","year":"2021","journal-title":"IEEE ISSCC"}],"event":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","location":"Milan, Italy","start":{"date-parts":[[2022,9,19]]},"end":{"date-parts":[[2022,9,22]]}},"container-title":["ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9911257\/9911222\/09911359.pdf?arnumber=9911359","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,27]],"date-time":"2023-02-27T23:01:31Z","timestamp":1677538891000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9911359\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,9,19]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/esscirc55480.2022.9911359","relation":{},"subject":[],"published":{"date-parts":[[2022,9,19]]}}}