{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T19:11:19Z","timestamp":1776280279364,"version":"3.50.1"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,9,11]],"date-time":"2023-09-11T00:00:00Z","timestamp":1694390400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,11]],"date-time":"2023-09-11T00:00:00Z","timestamp":1694390400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,9,11]]},"DOI":"10.1109\/esscirc59616.2023.10268797","type":"proceedings-article","created":{"date-parts":[[2023,10,6]],"date-time":"2023-10-06T17:46:43Z","timestamp":1696614403000},"page":"365-368","source":"Crossref","is-referenced-by-count":11,"title":["True Voltage-Mode NRZ VCSEL Transmitter enabling 60 Gbit\/s at 0.37 pJ\/bit in 22 nm FDSOI"],"prefix":"10.1109","author":[{"given":"Urs","family":"Hecht","sequence":"first","affiliation":[{"name":"TU Berlin, FG Mixed Signal Circuit Design, Einsteinufer 17,Berlin,Germany,10587"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Helia","family":"Ordouei","sequence":"additional","affiliation":[{"name":"TU Berlin, FG Mixed Signal Circuit Design, Einsteinufer 17,Berlin,Germany,10587"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nikolay","family":"Ledentsov","sequence":"additional","affiliation":[{"name":"Vertically Integrated Systems GmbH (VIS), Hardenbergstraße 7,Berlin,Germany,10623"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philipp","family":"Scholz","sequence":"additional","affiliation":[{"name":"TU Berlin, FG Mixed Signal Circuit Design, Einsteinufer 17,Berlin,Germany,10587"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Patrick","family":"Kurth","sequence":"additional","affiliation":[{"name":"TU Berlin, FG Mixed Signal Circuit Design, Einsteinufer 17,Berlin,Germany,10587"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nikolay","family":"Ledentsov","sequence":"additional","affiliation":[{"name":"Vertically Integrated Systems GmbH (VIS), Hardenbergstraße 7,Berlin,Germany,10623"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Friedel","family":"Gerfers","sequence":"additional","affiliation":[{"name":"TU Berlin, FG Mixed Signal Circuit Design, Einsteinufer 17,Berlin,Germany,10587"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref7","first-page":"1","article-title":"A compact electrooptical VCSEL model for high-speed IC design","author":"belfiore","year":"2016","journal-title":"in 2016 12th Conference on Ph D Research in Microelectronics and Electronics (PRIME)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/EuMIC.2017.8230689"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1364\/OFC.2022.Tu2D.3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/GEMIC.2019.8698167"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2870181"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3124289"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2014.2385671"}],"event":{"name":"ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)","location":"Lisbon, Portugal","start":{"date-parts":[[2023,9,11]]},"end":{"date-parts":[[2023,9,14]]}},"container-title":["ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10268677\/10268683\/10268797.pdf?arnumber=10268797","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,23]],"date-time":"2023-10-23T17:53:20Z","timestamp":1698083600000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10268797\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,11]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/esscirc59616.2023.10268797","relation":{},"subject":[],"published":{"date-parts":[[2023,9,11]]}}}