{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T05:19:18Z","timestamp":1751606358348,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,9,11]],"date-time":"2023-09-11T00:00:00Z","timestamp":1694390400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,11]],"date-time":"2023-09-11T00:00:00Z","timestamp":1694390400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,9,11]]},"DOI":"10.1109\/esscirc59616.2023.10268813","type":"proceedings-article","created":{"date-parts":[[2023,10,6]],"date-time":"2023-10-06T17:46:43Z","timestamp":1696614403000},"page":"369-372","source":"Crossref","is-referenced-by-count":2,"title":["A 0.82pJ\/b 50Gb\/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process"],"prefix":"10.1109","author":[{"given":"Milad Haghi","family":"Kashani","sequence":"first","affiliation":[{"name":"University of Toronto,ECE Department,Toronto,Canada"}]},{"given":"Hossein","family":"Shakiba","sequence":"additional","affiliation":[{"name":"Huawei Technologies,HiLink Department,Markham,Canada"}]},{"given":"Ali","family":"Sheikholeslami","sequence":"additional","affiliation":[{"name":"University of Toronto,ECE Department,Toronto,Canada"}]}],"member":"263","reference":[{"key":"ref7","first-page":"508","article-title":"High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects","author":"palermo","year":"2006","journal-title":"Proceedings of the 32nd European Solid-State Circuits Conference"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2018.2841841"},{"key":"ref3","first-page":"757","article-title":"A Scalable 32-56Gb\/s 0.56-1.28 pJ\/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS","volume":"57","author":"mansuri","year":"2022","journal-title":"IEEE JSSC"},{"key":"ref6","first-page":"268c","article-title":"A 64Gb\/s 2.29pJ\/b PAM-4 VCSEL Transmitter With 3Tap Asymmetric FFE in 65nm CMOS","author":"hwang","year":"2019"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3179678"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2584641"},{"key":"ref1","first-page":"2686","article-title":"A4×45 Gb\/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation","volume":"53","author":"khafaji","year":"2018","journal-title":"IEEE JSSC"}],"event":{"name":"ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)","start":{"date-parts":[[2023,9,11]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2023,9,14]]}},"container-title":["ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10268677\/10268683\/10268813.pdf?arnumber=10268813","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,23]],"date-time":"2023-10-23T17:53:06Z","timestamp":1698083586000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10268813\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,11]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/esscirc59616.2023.10268813","relation":{},"subject":[],"published":{"date-parts":[[2023,9,11]]}}}