{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T08:00:27Z","timestamp":1725523227419},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/essderc.2015.7324759","type":"proceedings-article","created":{"date-parts":[[2015,11,12]],"date-time":"2015-11-12T23:03:10Z","timestamp":1447369390000},"page":"242-245","source":"Crossref","is-referenced-by-count":1,"title":["Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR"],"prefix":"10.1109","author":[{"given":"Gaspard","family":"Hiblot","sequence":"first","affiliation":[]},{"given":"Quentin","family":"Rafhay","sequence":"additional","affiliation":[]},{"given":"Loic","family":"Gaben","sequence":"additional","affiliation":[]},{"given":"Gerard","family":"Ghibaudo","sequence":"additional","affiliation":[]},{"given":"Frederic","family":"Boeuf","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.848098"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810054"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2368395"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831796"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.661211"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2002.993112"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2012.6404393"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.911338"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2015.02.001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2013.6716523"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2013.6650605"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.895241"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2187454"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2013.10.007"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ULIS.2012.6193351"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"3.8.1","DOI":"10.1109\/IEDM.2014.7046977","article-title":"High performance 14nm SOI FinFET CMOS technology with 0.0174 ?m2embedded DRAM and 15 levels of Cu metallization","author":"lin","year":"2014","journal-title":"Electron Devices Meeting (IEDM) 2014 IEEE International"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2388788"}],"event":{"name":"ESSDERC 2015 - 45th European Solid-State Device Research Conference","start":{"date-parts":[[2015,9,14]]},"location":"Graz, Austria","end":{"date-parts":[[2015,9,18]]}},"container-title":["2015 45th European Solid State Device Research Conference (ESSDERC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7300344\/7324696\/07324759.pdf?arnumber=7324759","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T23:32:51Z","timestamp":1498260771000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7324759\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/essderc.2015.7324759","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}