{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T02:24:53Z","timestamp":1769912693373,"version":"3.49.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/essderc.2016.7599605","type":"proceedings-article","created":{"date-parts":[[2016,10,20]],"date-time":"2016-10-20T21:00:55Z","timestamp":1476997255000},"page":"131-134","source":"Crossref","is-referenced-by-count":16,"title":["Towards high performance sub-10nm finW bulk FinFET technology"],"prefix":"10.1109","author":[{"given":"T.","family":"Chiarella","sequence":"first","affiliation":[]},{"given":"S.","family":"Kubicek","sequence":"additional","affiliation":[]},{"given":"E.","family":"Rosseel","sequence":"additional","affiliation":[]},{"given":"R.","family":"Ritzenthaler","sequence":"additional","affiliation":[]},{"given":"A.","family":"Hikavyy","sequence":"additional","affiliation":[]},{"given":"P.","family":"Eyben","sequence":"additional","affiliation":[]},{"given":"A.","family":"De Keersgieter","sequence":"additional","affiliation":[]},{"given":"L-A.","family":"Ragnarsson","sequence":"additional","affiliation":[]},{"given":"M.-S","family":"Kim","sequence":"additional","affiliation":[]},{"given":"S.-A","family":"Chew","sequence":"additional","affiliation":[]},{"given":"T.","family":"Schram","sequence":"additional","affiliation":[]},{"given":"S.","family":"Demuynck","sequence":"additional","affiliation":[]},{"given":"M.","family":"Cupak","sequence":"additional","affiliation":[]},{"given":"L.","family":"Rijnders","sequence":"additional","affiliation":[]},{"given":"M.","family":"Dehan","sequence":"additional","affiliation":[]},{"given":"N.","family":"Horiguchi","sequence":"additional","affiliation":[]},{"given":"J.","family":"Mitard","sequence":"additional","affiliation":[]},{"given":"D.","family":"Mocuta","sequence":"additional","affiliation":[]},{"given":"A.","family":"Mocuta","sequence":"additional","affiliation":[]},{"given":"A. V-Y.","family":"Thean","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2010.5618377"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573392"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2009.5159323"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2008.4588544"},{"key":"ref14","article-title":"Effects of the fin width variation on the performance of 16 nm FinFETs with rouad fin corners and tapered fin shape","author":"wan","year":"2014","journal-title":"ICSE"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2015.7165884"},{"key":"ref16","article-title":"Scalpel Soft Retrace Scanning Spreading Resistance Microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET","author":"eyben","year":"2015","journal-title":"IEDM"},{"key":"ref4","article-title":"Self-Aligned Double Patterning of Ix nm FinFETs","author":"kim","year":"2013","journal-title":"ULIS"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339747"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.tsf.2015.09.068"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1149\/06406.0977ecst"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223691"},{"key":"ref7","article-title":"Highly Scalable Bulk FinFET Devices with Multi-VT Options by Conductive Metal Gate Stack Tuning for the 10-nm Node and Beyond","author":"ragnarsson","year":"2014","journal-title":"VLSI"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"key":"ref1","article-title":"A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size","author":"natarajan","year":"2014","journal-title":"VLSI"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2005.1546591"}],"event":{"name":"ESSDERC 2016 - 46th European Solid-State Device Research Conference","location":"Lausanne, Switzerland","start":{"date-parts":[[2016,9,12]]},"end":{"date-parts":[[2016,9,15]]}},"container-title":["2016 46th European Solid-State Device Research Conference (ESSDERC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7584557\/7598672\/07599605.pdf?arnumber=7599605","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,11,16]],"date-time":"2016-11-16T14:21:06Z","timestamp":1479306066000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7599605\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/essderc.2016.7599605","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}