{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T04:28:21Z","timestamp":1725683301634},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/essderc.2016.7599625","type":"proceedings-article","created":{"date-parts":[[2016,10,20]],"date-time":"2016-10-20T17:00:55Z","timestamp":1476982855000},"page":"218-221","source":"Crossref","is-referenced-by-count":5,"title":["Impact of intermediate BEOL technology on standard cell performances of 3D VLSI"],"prefix":"10.1109","author":[{"given":"M.","family":"Brocard","sequence":"first","affiliation":[]},{"given":"G.","family":"Berhault","sequence":"additional","affiliation":[]},{"given":"S.","family":"Thuries","sequence":"additional","affiliation":[]},{"given":"F.","family":"Clermidy","sequence":"additional","affiliation":[]},{"given":"P.","family":"Batude","sequence":"additional","affiliation":[]},{"given":"C.","family":"Fenouillet-Beranger","sequence":"additional","affiliation":[]},{"given":"L.","family":"Brunet","sequence":"additional","affiliation":[]},{"given":"F.","family":"Andrieu","sequence":"additional","affiliation":[]},{"given":"F.","family":"Deprat","sequence":"additional","affiliation":[]},{"given":"J.","family":"Lacord","sequence":"additional","affiliation":[]},{"given":"O.","family":"Rozeau","sequence":"additional","affiliation":[]},{"given":"G.","family":"Cibrario","sequence":"additional","affiliation":[]},{"given":"O.","family":"Billoint","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2015.7333504"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2723573"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2015.102"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2015.7334472"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479040"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2014.6948770"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223698"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593188"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131506"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.7567\/SSDM.2015.K-4-3","article-title":"W and Copper Interconnection Stability for 3D VLSI CoolCube Integration","author":"fenouillet-beranger","year":"2015","journal-title":"2015 International Conference on Solid State Devices and Materials (SSDM)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717779"}],"event":{"name":"ESSDERC 2016 - 46th European Solid-State Device Research Conference","start":{"date-parts":[[2016,9,12]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2016,9,15]]}},"container-title":["2016 46th European Solid-State Device Research Conference (ESSDERC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7584557\/7598672\/07599625.pdf?arnumber=7599625","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,14]],"date-time":"2019-09-14T17:33:35Z","timestamp":1568482415000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7599625\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/essderc.2016.7599625","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}