{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T16:51:41Z","timestamp":1730220701550,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/essderc.2018.8486857","type":"proceedings-article","created":{"date-parts":[[2018,10,18]],"date-time":"2018-10-18T14:50:05Z","timestamp":1539874205000},"page":"158-161","source":"Crossref","is-referenced-by-count":7,"title":["Scaling CMOS beyond Si FinFET: an analog\/RF perspective"],"prefix":"10.1109","author":[{"given":"B.","family":"Parvais","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Hellings","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Simicic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Weckx","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Mitard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Jang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Deshpande","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"van Liempc","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Veloso","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Vandooren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Waldron","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Wambacq","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Collaert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Verkest","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131543"},{"key":"ref11","article-title":"Strained Germanium GAA pFETs: An In-depth Study of Corner Devices and Comparison With State-Of-the-Art Si GAA FETs","author":"mitard","year":"2018","journal-title":"VLSI Symp"},{"key":"ref12","first-page":"91101","article-title":"III\/V nano ridge structures for optical applications on patterned 300mm silicon substrate","volume":"109","author":"kunert","year":"2016","journal-title":"APL"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2014.6894349"},{"key":"ref14","article-title":"3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525&#x00B0;C with improved reliability","author":"vandooren","year":"0","journal-title":"VLSI Symp '18"},{"key":"ref15","article-title":"Junctionless Gate-All-Around Lateral and Vertical Nanowire FETs with Simplified Processing for Advanced Logic and AnalogiRF Applications and Scaled SRAM Cells","author":"veloso","year":"0","journal-title":"2016 IEEE Symp VLSI"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2776838"},{"key":"ref3","first-page":"ti48","article-title":"RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs","author":"ragnarsson","year":"2015","journal-title":"VLSI Symp"},{"key":"ref6","article-title":"Record 47 mV\/dec Top-Down Vertical Nanowire InGaAs\/GaAsSb Tunnel FETs","author":"alian","year":"2018","journal-title":"VLSI Symp"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338394"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338379"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2404293"},{"key":"ref2","article-title":"Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells","author":"garcia bardon","year":"2018","journal-title":"VLSI Symp"},{"key":"ref1","first-page":"20. 4. 1","article-title":"Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology","author":"yakimets","year":"2017","journal-title":"IEDM"},{"key":"ref9","article-title":"Si\/SiGe\/Si\/SiGe\/Si superlattice 1\/O finFETs in a horizontal, vertically-stacked nanowire technology","author":"hellings","year":"2018","journal-title":"accepted VLSI Symp"}],"event":{"name":"48th European Solid-State Device Research Conference (ESSDERC 2018)","start":{"date-parts":[[2018,9,3]]},"location":"Dresden","end":{"date-parts":[[2018,9,6]]}},"container-title":["2018 48th European Solid-State Device Research Conference (ESSDERC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8476153\/8486846\/08486857.pdf?arnumber=8486857","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T23:19:02Z","timestamp":1598224742000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8486857\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/essderc.2018.8486857","relation":{},"subject":[],"published":{"date-parts":[[2018,9]]}}}