{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,7]],"date-time":"2025-08-07T09:07:22Z","timestamp":1754557642221},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/essderc.2018.8486875","type":"proceedings-article","created":{"date-parts":[[2018,10,18]],"date-time":"2018-10-18T18:50:05Z","timestamp":1539888605000},"page":"170-173","source":"Crossref","is-referenced-by-count":5,"title":["Why SPICE Is Just As Good And Just As Bad For IC Design As It Was 40 Years Ago"],"prefix":"10.1109","author":[{"given":"Laurence W.","family":"Nagel","sequence":"first","affiliation":[]},{"given":"Colin C.","family":"McAndrew","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"SPECTRE","year":"0","key":"ref10"},{"journal-title":"SmartSpice","year":"0","key":"ref11"},{"journal-title":"Xyce","year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2419626"},{"key":"ref14","article-title":"Statistical transistor SPICE modeling in advanced CMOS technologies","author":"krick","year":"2008","journal-title":"IEEE\/ACM Workshop on Compact Variability Modeling"},{"key":"ref15","first-page":"219","article-title":"Cor-ner models: inaccurate at best, and it only gets worst","author":"mcandrew","year":"2013","journal-title":"Proc Custom Integrated Circuits Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280743"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2015.7208509"},{"key":"ref18","first-page":"27","article-title":"ADMS-automated device model synthesizer","author":"lemaitre","year":"2002","journal-title":"Proc IEEE CICC"},{"key":"ref4","article-title":"Simulation program with integrated circuit emphasis (SPICE)","author":"nagel","year":"1973","journal-title":"16th Midwest Symp Circuit Theory"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1971.1050166"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1969.1082965"},{"journal-title":"SPICE2 A computer program to simulate semiconductor circuits","year":"1975","author":"nagel","key":"ref5"},{"key":"ref8","article-title":"MAPP: the Berkeley model and algorithm prototyping platform","author":"wang","year":"2015","journal-title":"Proc IEEE CICC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672065"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1971.1050168"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1971.1050153"},{"year":"0","key":"ref9"}],"event":{"name":"48th European Solid-State Device Research Conference (ESSDERC 2018)","start":{"date-parts":[[2018,9,3]]},"location":"Dresden","end":{"date-parts":[[2018,9,6]]}},"container-title":["2018 48th European Solid-State Device Research Conference (ESSDERC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8476153\/8486846\/08486875.pdf?arnumber=8486875","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T03:19:19Z","timestamp":1598239159000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8486875\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/essderc.2018.8486875","relation":{},"subject":[],"published":{"date-parts":[[2018,9]]}}}