{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:25:37Z","timestamp":1729635937049,"version":"3.28.0"},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/estimedia.2013.6704505","type":"proceedings-article","created":{"date-parts":[[2014,1,10]],"date-time":"2014-01-10T20:04:58Z","timestamp":1389384298000},"page":"68-77","source":"Crossref","is-referenced-by-count":0,"title":["System-level optimization of on-chip communication using express links for throughput constrained MPSoCs"],"prefix":"10.1109","author":[{"given":"Haseeb","family":"Bokhari","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haris","family":"Javaid","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.911337"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888284"},{"key":"18","article-title":"Leveraging application-level requirements in the design of a NoC for a 4G SoC: A case study","author":"beraha","year":"2010","journal-title":"Proceedings of the conference on Design Automation and Test in Europe"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456953"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-92990-1_15"},{"key":"13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1297666.1297677","article-title":"Analysis and optimization of prediction-based flow control in networks-on-chip","volume":"13","author":"ogras","year":"2008","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176721"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483953"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/2076501.2076505"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/12.83652"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228597"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/SPDP.1996.570385"},{"key":"23","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1109\/MM.2008.18","article-title":"Toward ideal on-chip communication using express virtual channels","volume":"28","author":"kumar","year":"2008","journal-title":"Micro IEEE"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187490"},{"key":"25","first-page":"1","article-title":"MAPS: Mapping concurrent dataflow applications to heterogeneous mpsocs","author":"castrillon","year":"2011","journal-title":"Industrial Informatics IEEE Transactions on"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-009-0351-6"},{"key":"27","doi-asserted-by":"crossref","first-page":"408","DOI":"10.1109\/TCAD.2006.884487","article-title":"A framework for cosynthesis of memory and communication architectures for mpsoc","volume":"26","author":"sudeep","year":"2007","journal-title":"Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on"},{"key":"28","doi-asserted-by":"crossref","first-page":"564","DOI":"10.1145\/1142980.1142983","article-title":"Computation and communication refinement for multiprocessor SoC design: A system-level perspective","volume":"11","author":"marculescu","year":"2004","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/1168919.1168877"},{"key":"3","first-page":"471","article-title":"The semantics of a simple language for parallel programming","author":"kahn","year":"1974","journal-title":"Proceedings of IFIP Congress 74 Amsterdam the Netherlands"},{"journal-title":"Multiprocessor Systems-on-Chips","year":"2004","author":"jerraya","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771806"},{"key":"1","doi-asserted-by":"crossref","first-page":"693","DOI":"10.1109\/TVLSI.2006.878263","article-title":"It's a small world after all NoC performance optimization via long-range link insertion","volume":"14","author":"ogras","year":"2006","journal-title":"Very Large Scale Integration (VLSI) Systems IEEE Transactions on"},{"year":"0","key":"30"},{"year":"0","key":"7"},{"year":"0","key":"6"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/HSC.1998.666245"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878978"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071467"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030439"},{"year":"0","key":"9"},{"year":"0","key":"8"}],"event":{"name":"2013 IEEE 11th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia)","start":{"date-parts":[[2013,10,3]]},"location":"Montreal, QC, Canada","end":{"date-parts":[[2013,10,4]]}},"container-title":["The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6689794\/6704489\/06704505.pdf?arnumber=6704505","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T05:50:17Z","timestamp":1498110617000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6704505\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/estimedia.2013.6704505","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}