{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T02:27:33Z","timestamp":1774751253872,"version":"3.50.1"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/estimedia.2013.6704506","type":"proceedings-article","created":{"date-parts":[[2014,1,10]],"date-time":"2014-01-10T15:04:58Z","timestamp":1389366298000},"page":"78-87","source":"Crossref","is-referenced-by-count":2,"title":["Design and evaluation of a media-oriented vector processor with a multi-banked cache memory"],"prefix":"10.1109","author":[{"family":"Ye Gao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naoki","family":"Shoji","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryusuke","family":"Egawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Takizawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroaki","family":"Kobayashi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501193"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176257"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193936"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859664"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.110"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.124"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.9"},{"key":"16","author":"hennessy","year":"2011","journal-title":"Computer Architecture A Quantitative Approach Fifth Edition"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/CoolChips.2013.6547923"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19448-1_8"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003586"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2008.100"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"20","article-title":"P6 family of processors hardware developer's manual","year":"1998","journal-title":"Intel White Paper"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"25","year":"2013","journal-title":"DDR3 SDRAM System-Power Calculator"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2005.1525999"},{"key":"28","article-title":"The compilers and mpi library for sx-9","author":"yokoya","year":"2008","journal-title":"NEC Corporation Tech Rep"},{"key":"29","year":"2011","journal-title":"Intel 64 and IA-32 Architectures Optimization Reference Manual"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362646"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2012.6467205"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751448"},{"key":"1","year":"2012","journal-title":"BT 2020 Parameter Values for Ultra-high Definition Television Systems for Production and International Programme Exchange"},{"key":"30","article-title":"The best way to achieve vector-like performance","author":"smith","year":"1994","journal-title":"International Symposium on Computer Architecture"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751453"},{"key":"6","article-title":"NECs solution portfolio","author":"rudolf","year":"2010","journal-title":"Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis - SC '09"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645807"},{"key":"5","first-page":"29","article-title":"Packaging technology of the sx-9","volume":"3","author":"umezawa","year":"2008","journal-title":"NEC Technical Journal"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840415"},{"key":"4","first-page":"15","article-title":"Hardware technology of the sx-9 (1): Main system","volume":"3","author":"nakazato","year":"2008","journal-title":"NEC Technical Journal"},{"key":"9","author":"bienia","year":"2011","journal-title":"Benchmarking Modern Multiprocessors"},{"key":"8","first-page":"138","article-title":"A comparison between processor architectures for multimedia applications","author":"shahbahrami","year":"2004","journal-title":"Proc 15th Annual Workshop on Circuits Systems and Signal Processing"}],"event":{"name":"2013 IEEE 11th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia)","location":"Montreal, QC, Canada","start":{"date-parts":[[2013,10,3]]},"end":{"date-parts":[[2013,10,4]]}},"container-title":["The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6689794\/6704489\/06704506.pdf?arnumber=6704506","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T14:13:52Z","timestamp":1490192032000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6704506\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/estimedia.2013.6704506","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}