{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,31]],"date-time":"2025-07-31T00:30:02Z","timestamp":1753921802607,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/ets.2012.6233005","type":"proceedings-article","created":{"date-parts":[[2012,7,19]],"date-time":"2012-07-19T23:41:10Z","timestamp":1342741270000},"page":"1-6","source":"Crossref","is-referenced-by-count":9,"title":["Fast error detection through efficient use of hardwired resources in FPGAs"],"prefix":"10.1109","author":[{"given":"Gabriel L.","family":"Nazar","sequence":"first","affiliation":[]},{"given":"Luigi","family":"Carro","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Command Line Tools User Guide","year":"0","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/RADECS.2005.4365640"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.82"},{"journal-title":"Virtex-5 FPGA User Guide","year":"0","key":"15"},{"key":"16","first-page":"878","article-title":"Design of dynamically checked computers","volume":"2","author":"carter","year":"1968","journal-title":"Proc IFIP Congress"},{"journal-title":"TMRTool Product Brief","year":"0","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/92.678870"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.891102"},{"journal-title":"Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory","year":"0","author":"carmichael","key":"12"},{"journal-title":"BLIF2VHDL","year":"0","author":"minkovich","key":"21"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2009.9"},{"journal-title":"SEU Strategies for Virtex-5 FPGAs","year":"0","author":"chapman","key":"20"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2011.5981537"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/92.736139"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2011.27"},{"journal-title":"Stratix V Device Handbook","year":"0","key":"6"},{"journal-title":"7 Series FPGAs Overview","year":"0","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723155"},{"journal-title":"Virtex-5 FPGA Configuration User Guide","year":"0","key":"9"},{"key":"8","first-page":"650","article-title":"Designing fault tolerant systems into sram-based fpgas","author":"lima","year":"2003","journal-title":"Design Automation Conference"}],"event":{"name":"2012 17th IEEE European Test Symposium (ETS)","start":{"date-parts":[[2012,5,28]]},"location":"Annecy, France","end":{"date-parts":[[2012,5,31]]}},"container-title":["2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6222773\/6232988\/06233005.pdf?arnumber=6233005","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T16:22:06Z","timestamp":1490113326000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6233005\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/ets.2012.6233005","relation":{},"subject":[],"published":{"date-parts":[[2012,5]]}}}