{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,5]],"date-time":"2026-07-05T03:16:49Z","timestamp":1783221409580,"version":"3.54.6"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/ets.2016.7519310","type":"proceedings-article","created":{"date-parts":[[2016,7,25]],"date-time":"2016-07-25T20:38:17Z","timestamp":1469479097000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system"],"prefix":"10.1109","author":[{"given":"Jean","family":"Durupt","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pascal","family":"Vivet","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Juergen","family":"Schloeffel","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.83"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2015.11"},{"key":"ref13","article-title":"Automated Test Creation For Mixed Signal IP Using IJTAG","author":"keim","year":"0","journal-title":"White Paper Mentor Graphics"},{"key":"ref4","article-title":"A Scan Island Based Design Enabling Prebond Testability in Die Stacked Microprocessors","author":"lewis","year":"0","journal-title":"ITC '07"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2424422"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090661"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601902"},{"key":"ref8","article-title":"A Standardizable 3D DfT Architecture","author":"marinissen","year":"0","journal-title":"3D-TEST'10"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469556"},{"key":"ref2","article-title":"The “active-interposer” concept for highperformance chip-to-chip connections","author":"ch\u00e9ramy","year":"2014","journal-title":"Chip Scale Review"},{"key":"ref1","article-title":"Active-Lite Interposer for 2.5 & 3D Integration","author":"hellings","year":"0","journal-title":"2015 Symposia on VLSI Technology and Circuits (VLSI'15)"},{"key":"ref9","article-title":"3D Design for Test Architectures Based on IEEE P1687","author":"fkih","year":"0","journal-title":"Workshop 3D Test'13"}],"event":{"name":"2016 IEEE European Test Symposium (ETS)","location":"Amsterdam, Netherlands","start":{"date-parts":[[2016,5,23]]},"end":{"date-parts":[[2016,5,27]]}},"container-title":["2016 21th IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7510593\/7519270\/07519310.pdf?arnumber=7519310","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,26]],"date-time":"2016-09-26T14:32:23Z","timestamp":1474900343000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7519310\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ets.2016.7519310","relation":{},"subject":[],"published":{"date-parts":[[2016,5]]}}}