{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,5]],"date-time":"2026-07-05T03:16:39Z","timestamp":1783221399093,"version":"3.54.6"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/ets.2016.7519330","type":"proceedings-article","created":{"date-parts":[[2016,7,25]],"date-time":"2016-07-25T20:38:17Z","timestamp":1469479097000},"page":"1-10","source":"Crossref","is-referenced-by-count":37,"title":["IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs"],"prefix":"10.1109","author":[{"given":"Erik Jan","family":"Marinissen","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Teresa","family":"McLaurin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Hailong Jiao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","year":"2005","journal-title":"IEEE Computer Society"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469556"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751450"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5269-9"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401569"},{"key":"ref15","year":"2014"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.83"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.1007\/0-387-34609-0","volume":"35","author":"da silva","year":"2006","journal-title":"Frontiers in Electronics Testing"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.21"},{"key":"ref4","article-title":"New Paradigm Shift in 3-D Design and Testing","author":"rearick","year":"2015","journal-title":"Digest of IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST)"},{"key":"ref3","article-title":"Wide-IO DRAM-ST-Ericsson's First Mobile Processor Using TSV 3D-IC Technology","author":"freund","year":"2011","journal-title":"CDNLive! EMEA"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2419227"},{"key":"ref5","first-page":"1277","article-title":"Challenges and Emerging Solutions in Testing TSV-Based 2.5D- and 3D-Stacked ICs","author":"marinissen","year":"2012","journal-title":"Proceedings Design Automation and Test in Europe (DATE)"},{"key":"ref8","year":"2013","journal-title":"IEEE Computer Society"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702351"},{"key":"ref2","author":"saban","year":"2010","journal-title":"Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity Bandwidth and Power Efficiency"},{"key":"ref1","author":"jones","year":"2010","journal-title":"Technical Viability of Stacked Silicon Interconnect Technology"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2013.29"}],"event":{"name":"2016 IEEE European Test Symposium (ETS)","location":"Amsterdam, Netherlands","start":{"date-parts":[[2016,5,23]]},"end":{"date-parts":[[2016,5,27]]}},"container-title":["2016 21th IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7510593\/7519270\/07519330.pdf?arnumber=7519330","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T19:07:47Z","timestamp":1498331267000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7519330\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/ets.2016.7519330","relation":{},"subject":[],"published":{"date-parts":[[2016,5]]}}}