{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T20:32:11Z","timestamp":1783715531579,"version":"3.55.0"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/ets.2019.8791536","type":"proceedings-article","created":{"date-parts":[[2019,8,8]],"date-time":"2019-08-08T19:48:50Z","timestamp":1565293730000},"page":"1-6","source":"Crossref","is-referenced-by-count":7,"title":["Hardware-Based Aging Mitigation Scheme for Memory Address Decoder"],"prefix":"10.1109","author":[{"given":"Daniel","family":"Kraak","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Innocent","family":"Agbo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mottaqiallah","family":"Taouil","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Said","family":"Hamdioui","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pieter","family":"Weckx","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stefan","family":"Cosemans","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Francky","family":"Catthoor","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2625809"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2643618"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2013.6727124"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927107"},{"key":"ref14","author":"hughes","year":"2009","journal-title":"Detection of address decoder faults"},{"key":"ref15","author":"ramaraju","year":"2013","journal-title":"Word line fault detection"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488856"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784501"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342003"},{"key":"ref19","article-title":"Methodology for application-dependent degradation analysis of memory timing","year":"2019","journal-title":"DATE"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743133"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320885"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.73"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386943"},{"key":"ref8","first-page":"1","article-title":"Bias temperature instability analysis of finfet based sram cells","author":"khan","year":"2014","journal-title":"DATE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.907409"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311888"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059010"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref22","year":"0","journal-title":"Nanotime - transistor-level static timing analysis solution for custom designs"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"Spec cpu2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"SIGARCH Comput Archit News"}],"event":{"name":"2019 IEEE European Test Symposium (ETS)","location":"Baden-Baden, Germany","start":{"date-parts":[[2019,5,27]]},"end":{"date-parts":[[2019,5,31]]}},"container-title":["2019 IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8784130\/8791505\/08791536.pdf?arnumber=8791536","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T17:54:12Z","timestamp":1658080452000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8791536\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/ets.2019.8791536","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}