{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,12]],"date-time":"2026-05-12T16:39:37Z","timestamp":1778603977334,"version":"3.51.4"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,5]]},"DOI":"10.1109\/ets48528.2020.9131554","type":"proceedings-article","created":{"date-parts":[[2020,7,2]],"date-time":"2020-07-02T21:06:26Z","timestamp":1593723986000},"page":"1-2","source":"Crossref","is-referenced-by-count":3,"title":["Detection of Rowhammer Attacks in SoCs with FPGAs"],"prefix":"10.1109","author":[{"given":"Rana","family":"Elnaggar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siyuan","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peilin","family":"Song","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"1","article-title":"A security vulnerability analysis of SoCFPGA architectures","author":"chaudhuri","year":"0","journal-title":"Proc ACM DAC"},{"key":"ref3","year":"0","journal-title":"PL-to-PS SDRAM in Xilinx Zynq-7000"},{"key":"ref10","year":"0","journal-title":"Using SDRAM in DE1SoC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3214292.3214299"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2954679.2872390"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665726"},{"key":"ref7","article-title":"Physical-to-row address mapping","year":"0"},{"key":"ref2","year":"0","journal-title":"MemoryinerconnectsinIntelFPGA-SoCs"},{"key":"ref9","year":"0","journal-title":"ISSI SDRAM DDR3 Features"},{"key":"ref1","year":"0","journal-title":"Architecture Brief What is an SoC FPGA?"}],"event":{"name":"2020 IEEE European Test Symposium (ETS)","location":"Tallinn, Estonia","start":{"date-parts":[[2020,5,25]]},"end":{"date-parts":[[2020,5,29]]}},"container-title":["2020 IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9125440\/9131553\/09131554.pdf?arnumber=9131554","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:53:45Z","timestamp":1656345225000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9131554\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ets48528.2020.9131554","relation":{},"subject":[],"published":{"date-parts":[[2020,5]]}}}