{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T21:43:02Z","timestamp":1767908582907,"version":"3.49.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,24]],"date-time":"2021-05-24T00:00:00Z","timestamp":1621814400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,24]],"date-time":"2021-05-24T00:00:00Z","timestamp":1621814400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5,24]]},"DOI":"10.1109\/ets50041.2021.9465403","type":"proceedings-article","created":{"date-parts":[[2021,6,29]],"date-time":"2021-06-29T20:23:46Z","timestamp":1624998226000},"page":"1-4","source":"Crossref","is-referenced-by-count":11,"title":["Unsupervised Learning in Test Generation for Digital Integrated Circuits"],"prefix":"10.1109","author":[{"given":"Soham","family":"Roy","sequence":"first","affiliation":[{"name":"Auburn University,Department of Electrical and Computer Engineering,Auburn,AL,36849-5201"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Spencer K.","family":"Millican","sequence":"additional","affiliation":[{"name":"Auburn University,Department of Electrical and Computer Engineering,Auburn,AL,36849-5201"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vishwani D.","family":"Agrawal","sequence":"additional","affiliation":[{"name":"Auburn University,Department of Electrical and Computer Engineering,Auburn,AL,36849-5201"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/318013.318101"},{"key":"ref11","article-title":"Machine Intelligence for Efficient Test Pattern Generation","author":"roy","year":"2020","journal-title":"Proceedings of the IEEE International Test Conference"},{"key":"ref12","article-title":"Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator","author":"roy","year":"2021","journal-title":"Proc 34th International Conference on VLSI Design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1080\/14786440109462720"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"417","DOI":"10.1037\/h0071325","article-title":"Analysis of a complex of statistical variables into principal components","volume":"24","author":"hotelling","year":"1933","journal-title":"Journal of Educational Psychology"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1002\/0471725331"},{"key":"ref16","author":"jolliffe","year":"2002","journal-title":"Principal Component Analysis"},{"key":"ref17","author":"diamantaras","year":"1996","journal-title":"Principal component Neural Networks Theory and Applications"},{"key":"ref18","author":"flury","year":"1988","journal-title":"Common Principal Components and Related Models"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1198\/jcgs.2010.08127"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NATW.2019.8758727"},{"key":"ref3","first-page":"1","article-title":"Special Session – Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits","author":"roy","year":"2021","journal-title":"Proc IEEE VLSI Test Symposium (VTS’21)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS47505.2019.000-7"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-020-05859-4"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675757"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3958-2"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2018.8400701"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1002\/widm.1360"},{"key":"ref9","first-page":"1","article-title":"What Heuristics are Best for PODEM?","author":"patel","year":"1985","journal-title":"Proc First International Workshop on VLSI Design"},{"key":"ref20","first-page":"221","article-title":"On Testability Analysis of Combinational Circuits","author":"brglez","year":"1984","journal-title":"Proc Int Symp Circuits and Systems"},{"key":"ref22","first-page":"677","article-title":"A Neutral Netlist of 10 Combinational Benchmark Circuits and a Targeted Translator in FORTRAN","author":"brglez","year":"1985","journal-title":"Proceedings of the IEEE Int Symposium on Circuits and Systems (ISCAS)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084687"},{"key":"ref24","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"}],"event":{"name":"2021 IEEE European Test Symposium (ETS)","location":"Bruges, Belgium","start":{"date-parts":[[2021,5,24]]},"end":{"date-parts":[[2021,5,28]]}},"container-title":["2021 IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9465371\/9465372\/09465403.pdf?arnumber=9465403","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,3]],"date-time":"2022-08-03T00:03:38Z","timestamp":1659485018000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9465403\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5,24]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/ets50041.2021.9465403","relation":{},"subject":[],"published":{"date-parts":[[2021,5,24]]}}}