{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T16:22:04Z","timestamp":1779294124304,"version":"3.51.4"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,24]],"date-time":"2021-05-24T00:00:00Z","timestamp":1621814400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,24]],"date-time":"2021-05-24T00:00:00Z","timestamp":1621814400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5,24]]},"DOI":"10.1109\/ets50041.2021.9465468","type":"proceedings-article","created":{"date-parts":[[2021,6,29]],"date-time":"2021-06-29T20:23:46Z","timestamp":1624998226000},"page":"1-2","source":"Crossref","is-referenced-by-count":6,"title":["Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators"],"prefix":"10.1109","author":[{"given":"Ioannis","family":"Tsounis","sequence":"first","affiliation":[{"name":"University of Piraeus,Dept. of Informatics,Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Athanasios","family":"Papadimitriou","sequence":"additional","affiliation":[{"name":"University of Piraeus,Dept. of Informatics,Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mihalis","family":"Psarakis","sequence":"additional","affiliation":[{"name":"University of Piraeus,Dept. of Informatics,Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297312"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2671181"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744778"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920315"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897981"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2019.2923040"},{"key":"ref12","article-title":"JPEG Encoder Verilog","year":"0"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898057"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2020.2986235"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2018.2854412"},{"key":"ref9","article-title":"A Reconfigurable Approximate JPEG Encoder Implemented on FPGA Platform","author":"shrija","year":"2016","journal-title":"thesis"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"}],"event":{"name":"2021 IEEE European Test Symposium (ETS)","location":"Bruges, Belgium","start":{"date-parts":[[2021,5,24]]},"end":{"date-parts":[[2021,5,28]]}},"container-title":["2021 IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9465371\/9465372\/09465468.pdf?arnumber=9465468","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,3]],"date-time":"2022-08-03T00:03:39Z","timestamp":1659485019000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9465468\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5,24]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ets50041.2021.9465468","relation":{},"subject":[],"published":{"date-parts":[[2021,5,24]]}}}