{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T23:10:32Z","timestamp":1725664232964},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,5,22]],"date-time":"2023-05-22T00:00:00Z","timestamp":1684713600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,22]],"date-time":"2023-05-22T00:00:00Z","timestamp":1684713600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,5,22]]},"DOI":"10.1109\/ets56758.2023.10173866","type":"proceedings-article","created":{"date-parts":[[2023,7,12]],"date-time":"2023-07-12T17:20:34Z","timestamp":1689182434000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["SET Effects on Quasi Delay Insensitive and Synchronous Circuits"],"prefix":"10.1109","author":[{"given":"Zaheer","family":"Tabassam","sequence":"first","affiliation":[{"name":"Institute for Computer Engineering,TU Wien,Vienna,Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Steininger","sequence":"additional","affiliation":[{"name":"Institute for Computer Engineering,TU Wien,Vienna,Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"2014","journal-title":"Silvaco open-cell 15nm library v0 1_2014_06 from si2","key":"ref13"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/DAC.2002.1012660"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1007\/s10836-013-5385-9"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1016\/j.entcs.2009.07.032"},{"year":"2020","author":"spars\u00f8","journal-title":"Introduction to Asynchronous Circuit Design","key":"ref11"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1017\/CBO9780511674730"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/TCSII.2021.3100524"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/AICAS54282.2022.9869944"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TDSC.2008.37"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/ASYNC48570.2021.00012"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/IOLTS.2009.5195979"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/Austrochip51129.2020.9232985"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.29292\/jics.v16i2.518"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/SBCCI53441.2021.9530001"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/JPROC.2021.3067593"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/ASYNC48570.2021.00015"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.3390\/technologies10010023"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TNS.2020.3044659"}],"event":{"name":"2023 IEEE European Test Symposium (ETS)","start":{"date-parts":[[2023,5,22]]},"location":"Venezia, Italy","end":{"date-parts":[[2023,5,26]]}},"container-title":["2023 IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10173930\/10173940\/10173866.pdf?arnumber=10173866","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T17:55:40Z","timestamp":1690912540000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10173866\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5,22]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/ets56758.2023.10173866","relation":{},"subject":[],"published":{"date-parts":[[2023,5,22]]}}}