{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T15:30:07Z","timestamp":1773329407674,"version":"3.50.1"},"reference-count":86,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,5,22]],"date-time":"2023-05-22T00:00:00Z","timestamp":1684713600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,22]],"date-time":"2023-05-22T00:00:00Z","timestamp":1684713600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002701","name":"Ministry of Education","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002701","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100011033","name":"Agencia Estatal de Investigaci\u00f3n","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100011033","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,5,22]]},"DOI":"10.1109\/ets56758.2023.10174099","type":"proceedings-article","created":{"date-parts":[[2023,7,12]],"date-time":"2023-07-12T17:20:34Z","timestamp":1689182434000},"page":"1-10","source":"Crossref","is-referenced-by-count":11,"title":["A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors"],"prefix":"10.1109","author":[{"given":"Jens","family":"Anders","sequence":"first","affiliation":[{"name":"University of Stuttgart,Institute of Smart Sensors,Stuttgart,Germany"}]},{"given":"Pablo","family":"Andreu","sequence":"additional","affiliation":[{"name":"Universitat Politècnica de València,Spain"}]},{"given":"Bernd","family":"Becker","sequence":"additional","affiliation":[{"name":"University of Freiburg,Dpt. of Computer Science,Freiburg,Germany"}]},{"given":"Steffen","family":"Becker","sequence":"additional","affiliation":[{"name":"University of Stuttgart,Institute of Software Engineering,Stuttgart,Germany"}]},{"given":"Riccardo","family":"Cantoro","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Dpt. of Control and Computer Engineering,Turin,Italy"}]},{"given":"Nikolaos I.","family":"Deligiannis","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Dpt. of Control and Computer Engineering,Turin,Italy"}]},{"given":"Nourhan","family":"Elhamawy","sequence":"additional","affiliation":[{"name":"University of Stuttgart,Institute of Computer Architecture and Computer Engineering,Stuttgart,Germany"}]},{"given":"Tobias","family":"Faller","sequence":"additional","affiliation":[{"name":"University of Freiburg,Dpt. of Computer Science,Freiburg,Germany"}]},{"given":"Carles","family":"Hernandez","sequence":"additional","affiliation":[{"name":"Universitat Politècnica de València,Spain"}]},{"given":"Nele","family":"Mentens","sequence":"additional","affiliation":[{"name":"Leiden University,LIACS,Leiden,Netherlands"}]},{"given":"Mahnaz Namazi","family":"Rizi","sequence":"additional","affiliation":[{"name":"Leiden University,LIACS,Leiden,Netherlands"}]},{"given":"Ilia","family":"Polian","sequence":"additional","affiliation":[{"name":"University of Stuttgart,Institute of Computer Architecture and Computer Engineering,Stuttgart,Germany"}]},{"given":"Abolfazl","family":"Sajadi","sequence":"additional","affiliation":[{"name":"Leiden University,LIACS,Leiden,Netherlands"}]},{"given":"Mathias","family":"Sauer","sequence":"additional","affiliation":[{"name":"Advantest Europe,Boeblingen,Germany"}]},{"given":"Denis","family":"Schwachhofer","sequence":"additional","affiliation":[{"name":"University of Stuttgart,Institute of Computer Architecture and Computer Engineering,Stuttgart,Germany"}]},{"given":"Matteo Sonza","family":"Reorda","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Dpt. of Control and Computer Engineering,Turin,Italy"}]},{"given":"Todor","family":"Stefanov","sequence":"additional","affiliation":[{"name":"Leiden University,LIACS,Leiden,Netherlands"}]},{"given":"Ilya","family":"Tuzov","sequence":"additional","affiliation":[{"name":"Universitat Politècnica de València,Spain"}]},{"given":"Stefan","family":"Wagner","sequence":"additional","affiliation":[{"name":"University of Stuttgart,Institute of Software Engineering,Stuttgart,Germany"}]},{"given":"Nu\u0161a","family":"Zidari\u010d","sequence":"additional","affiliation":[{"name":"Leiden University,LIACS,Leiden,Netherlands"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3174125"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3457388.3458657"},{"key":"ref3","volume-title":"RISC-V ISA, Unprivileged Specification"},{"key":"ref4","article-title":"The Rocket Chip Generator","author":"Asanovi\u0107","year":"2016","journal-title":"EECS Department, University of California, Berkeley, USA, Tech. Rep. UCB\/EECS-2016-17"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2996616"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2897782"},{"key":"ref7","article-title":"SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine","author":"Zhao","year":"2020"},{"key":"ref8","volume-title":"Ibex documentation","year":"2023"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2017.8106976"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"key":"ref12","volume-title":"GitHub - SpinalHDL\/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation","year":"2018"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1587\/elex.17.20200282"},{"key":"ref14","volume-title":"GitHub - YosysHQ\/picorv32: PicoRV32 - A Size-Optimized RISC-V CPU"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CSTIC.2018.8369332"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3458903.3458904"},{"key":"ref17","volume-title":"EL2 SweRV RISC-V CoreTM 1.4","author":"Digital","year":"2020"},{"key":"ref18","article-title":"Area-Optimized RISC-V-Based Control System for 22nm FDSOI Analog and Mixed-Signal Test Chips","volume-title":"M.S. thesis, University of Twente","author":"Kruiper","year":"2023"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.3390\/info14020064"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2023.3246491"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ETS50041.2021.9465449"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.5"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2012.6233016"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ETS56758.2023.10174156"},{"key":"ref25","article-title":"Burn-In","volume-title":"IIRW","author":"Vollertsen"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/s38314-021-0691-y"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3252467"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2023.104775"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ATS49688.2020.9301557"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.2178387"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/vlsi-dat.2018.8373238"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ETS56758.2023.10173985"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/952532.952676"},{"key":"ref34","volume-title":"The Fuzzing Book","author":"Zeller","year":"2021"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502320"},{"key":"ref36","author":"Gaisler","year":"2011","journal-title":"Quad core LEON4 SPARC V8 processor - LEON4-NGMP-DRAFT - data sheet and users manual"},{"key":"ref37","journal-title":"AURIX Multicore 32-bit Microcontroller Family to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations"},{"issue":"99","key":"ref38","first-page":"1","article-title":"Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm Triple Core Lock-Step (TCLS) Architecture","author":"Iturbe","year":"2018","journal-title":"IEEE Design and Test"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-52794-5_4"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/DFT56152.2022.9962340"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2019.113447"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI51109.2021.00013"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3323917"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2021.114120"},{"key":"ref45","volume-title":"Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation","volume":"23","author":"Benso","year":"2003"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-38789-0_11"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/SIES.2015.7185039"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2015.04.002"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/rtas.2013.6531079"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2015.36"},{"key":"ref51","volume-title":"NOEL-V Processor","year":"2020"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/DSD51259.2020.00066"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS52814.2021.9486715"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ETS50041.2021.9465444"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/WF-IoT54382.2022.10152063"},{"key":"ref56","volume-title":"PULP Platform"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/3635161"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/18\/02\/C02032"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2915203"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2019.i4.17-61"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2021.105165"},{"key":"ref62","first-page":"1","article-title":"Extending a RISC-V core with an AES hardware accelerator to meet IOT constraints","volume-title":"SMACD \/ PRIME","author":"Zgheib"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2021.i1.109-136"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415728"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3162626"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715173"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i3.219-242"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116567"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2983185"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530552"},{"key":"ref71","article-title":"Versatile RISC-V ISA Galois Field arithmetic extension for cryptography and error-correction codes","volume-title":"CARRV","author":"Kuo"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i4.239-280"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2023.i1.193-237"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-68487-7_4"},{"key":"ref75","volume-title":"The RISC-V Cryptography Extensions, Volume I: Scalar & Entropy Source Instructions","author":"Marshall","year":"2022"},{"key":"ref76","volume-title":"The RISC-V Cryptography Extensions, Volume II: Vector Instructions","author":"Dockser","year":"2023"},{"key":"ref77","author":"Kiaei","year":"2020","journal-title":"Domain-Oriented Masked Instruction Set Architecture for RISC-V"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2021.i4.283-325"},{"key":"ref79","first-page":"1469","article-title":"COCO: Co-Design and Co-Verification of Masked Software Implementations on CPUs","volume-title":"USENIX","author":"Gigerl"},{"key":"ref80","article-title":"A survey on RISC-V security: Hardware and Architecture","author":"Lu","year":"2021"},{"key":"ref81","first-page":"857","article-title":"Sanctum: Minimal Hardware Extensions for Strong Software Isolation","volume-title":"USENIX","author":"Costan"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/CSF.2018.00011"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1145\/3342195.3387532"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2987617"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-020-00108-8"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2022.i1.630-656"}],"event":{"name":"2023 IEEE European Test Symposium (ETS)","location":"Venezia, Italy","start":{"date-parts":[[2023,5,22]]},"end":{"date-parts":[[2023,5,26]]}},"container-title":["2023 IEEE European Test Symposium (ETS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10173930\/10173940\/10174099.pdf?arnumber=10174099","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,1]],"date-time":"2024-03-01T13:18:36Z","timestamp":1709299116000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10174099\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5,22]]},"references-count":86,"URL":"https:\/\/doi.org\/10.1109\/ets56758.2023.10174099","relation":{},"subject":[],"published":{"date-parts":[[2023,5,22]]}}}